Irq Interrupt Sources; Fiq Interrupt Sources; Table 2: Overview Of Irq Interrupts; Table 3: Overview Of Fiq Interrupts - Siemens ERTEC200 Manual

The CPU accepts an IRQ-/FIQ request by reading the IRVEC/FIVEQ register. This register contains the binary-coded
vector number of the highest priority interrupt request at the moment. Each of the two interrupt vector registers can be
referenced using two different addresses. The interrupt controller interprets the reading of the vector register with the first
address as an "interrupt acknowledge". This causes the sequences for this interrupt to be implemented in the ICU logic.
Reading of the vector register with the second address is not linked to the "acknowledge function". This is primarily useful
for the debugging functions in order to read out the content of the interrupt vector register without starting the
acknowledge function of the interrupt controller.
2.9.7

IRQ Interrupt Sources

Interrupts from the following function groups of the ERTEC 200 are available to the IRQ interrupt controller:
Interrupt-Nr. Function Block
0 Timer
1 Timer
3:2 GPIO
5:4 GPIO
6 Timer
7 -----
8 UART
9 PHY0/1
10 SPI
11 SPI
12 IRT switch
13 IRT switch
14 -----
15 DMA

Table 2: Overview of IRQ Interrupts

2.9.8

FIQ Interrupt Sources

Interrupts from the following function groups of the ERTEC 200 are available to the FIQ interrupt controller:
Interrupt-Nr. Function Block
0 Watchdog
1 APB bus
2 Multilayer AHB
3 PLL-Status-Register
4 ARM-CPU
5 ARM-CPU
6 Optional
7 Optional

Table 3: Overview of FIQ Interrupts

(1) Access to non-existing addresses is detected by the individual function groups of the ERTEC 200 and triggers a
pulse with duration Tp = 2/50 MHz. For evaluation of this interrupt, the connected FIQ input must be specified as an
edge-triggered input.
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
IRQ Interrupts
Signal Name Default Setting
TIM_INT0 Rising edge
TIM_INT1 Rising edge
GPIO (1:0) Assignable
GPIO (31:30) Assignable
TIM_INT2 Rising edge
------
UART_INTR High level
P0/1_INTERP Rising edge
SSP_INTR Rising edge
SSP_ROR_INTR Rising edge
IRQ0_SP Rising edge
IRQ1_SP Rising edge
-----
DMA_INT Rising edge
FIQ Interrupts
Signal Name Default Setting
Rising edge
Rising edge
Rising edge
Rising edge
COMM_Rx Rising edge
COMM_Tx Rising edge
Optional from IRQ Rising edge
Optional from IRQ Rising edge
25
Comment
Timer 0
Timer 1
External input ERTEC 200 GPIO[1:0]
External input ERTEC 200
GPIO[31:30]
Timer 2
----- Reserved
Group interrupt UART
Interrupt von PHY 0/1
Group interrupt SPI
Receive overrun interrupt SPI
High-priority IRT interrupt
Low-priority IRT interrupt
----- Reserved
DMA controller, DMA transfer
complete
Comment
Access to non-existing address at
the APB (1)
Access to non-existing address at
the AHB (1)
Group interrupt of:
EMIF: I/O time-out
PLL: Loss state
PLL: Lock State
see system control register
"PLL_STAT_REG"
Receive comm channel interrupt
Transmit comm channel interrupt
User-programmable IRQ source
User-programmable IRQ source
ERTEC 200 Manual
Version 1.1.0