Philips LPC2119 User Manual page 162

Philips Semiconductors
ARM-based Microcontroller
Global Status Register (CANGSR - 0xE00x x008)
This register is read-only, except that the Error Counters can be written when the RM bit in the CANMOD register is 1. Bits not
listed read as 0 and should be written as 0.
Table 126: CAN Global Status Register (CANGSR - 0xE00x x008)
CANGSR Name Function
1: Receive Buffer Status -- a received message is available in the CANRFS,
CANRID, and if applicable the CANRDA and CANRDB registers. This bit is
0 RBS
cleared by the Release Receive Buffer command in CANCMR, if no subsequent
received message is available.
1: Data Overrun Status -- a message was lost because the preceding message to
this CAN controller was not read and released quickly enough.
1 DOS
0: No data overrun has occurred since the last Clear Data Overrun command was
written to CANCMR (or since Reset).
1: Transmit Buffer Status -- no transmit message is pending for this CAN controller
(in any of the 3 Tx buffers), and software may write to any of the CANTFI, CANTID,
CANTDA, and CANTDB registers.
2 TBS
0: as least one previously-queued message for this CAN controller has not yet
been sent, and therefore software should not write to the CANTFI, CANTID,
CANTDA, nor CANTDB registers of that (those) Tx buffer(s).
1: Transmit Complete Status -- all requested transmission(s) has (have) been
3 TCS successfully completed.
0: at least one requested transmission has not been successfully completed.
4 RS 1: Receive Status: the CAN controller is receiving a message.
5 TS 1: Transmit Status: The CAN controller is sending a message
1: Error Status: one or both of the Transmit and Receive Error Counters has
6 ES
reached the limit set in the Error Warning Limit register.
1: Bus Status: the CAN controller is currently prohibited from bus activity because
7 BS
the Transmit Error Counter reached its limiting value of 255.
23:16 RXERR The current value of the Rx Error Counter.
31:24 TXERR The current value of the Tx Error Counter.
Interrupt and Capture Register (CANICR - 0xE00x x00C)
Bits in this register indicate information about events on the CAN bus. This register is read-only. Bits not listed read as 0 and
should be written as 0. Bits 1-9 clear when they are read.
Bits 16-23 are captured when a bus error occurs. At the same time, if the BEIE bit in CANIER is 1, the BEI bit in this register is
set, and a CAN interrupt can occur. Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in
CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either of these bytes is captured, its value
will remain the same until it is read, at which time it is released to capture a new value.
As of Nov. 5, 2001, the clearing of bits 1-9 and the releasing of bits 16-23 and 24-31 all occur on any read from CANICR,
regardless of whether part or all of the register is read. This means that software should always read CANICR as a word, and
process and deal with all bits of the register as appropriate for the application.
CAN Controllers and Acceptance Filter
LPC2119/2129/2292/2294
162
Preliminary User Manual
Reset Value RM Set
0 0
0 0
1 X
1 0
0 0
0 0
0 0
0 0
0 X
0 X
January 08, 2004