Philips LPC2119 User Manual page 145

Philips Semiconductors
ARM-based Microcontroller
2
I C SCL Duty Cycle Registers (I2SCLH - 0xE001C010 and I2SCLL - 0xE001C014)
Software must set values for registers I2SCLH and I2SCLL to select the appropriate data rate. I2SCLH defines the number of
pclk cycles for SCL high, I2SCLL defines the number of pclk cycles for SCL low. The frequency is determined by the following
formula:
Bit Frequency = f / (I2SCLH + I2SCLL)
CLK
Where f is the frequency of pclk.
CLK
The values for I2SCLL and I2SCLH don't have to be the same. Software can set different duty cycles on SCL by setting these
two registers. But the value of the register must ensure that the data rate is in the I
the value of I2SCLL and I2SCLH has some restrictions. Each register value should be greater than or equal to 4.
2
Table 108: I C SCL High Duty Cycle Register (I2SCLH - 0xE001C010)
I2SCLH Function
15:0 Count
2
Table 109: I C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014)
I2SCLL Function
15:0 Count
Table 110: I2C Clock Rate Selections for VPB Clock Divider = 1
I2SCLL+
I2SCLH
8 -
10 -
25 -
50 320.0
75 213.333
100 160.0
160 100.0
200 80.0
320 50.0
400 40.0
510 31.373
800 20.0
1280 12.5
I2C Interface
Count for SCL HIGH time period selection
Count for SCL LOW time period selection
Bit Frequency (kHz) At f
16
-
-
-
400.0
266.667
200.0
125.0
100.0
62.5
50.0
39.216
25.0
15.625
2
C data rate range of 0 through 400KHz. So
Description
Description
(MHz) & VPB Clock Divider = 1
CCLK
20 40
-
-
-
-
-
400.0
250.0
200.0
125.0
100.0
78.431
50.0
31.25
145
Preliminary User Manual
LPC2119/2129/2292/2294
60
-
-
-
-
-
-
375.0
300.0
187.5
150.0
117.647
75.0
46.875
January 08, 2004
Reset
Value
0x 0004
Reset
Value
0x 0004