Pll (Phase Locked Loop) - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller

PLL (PHASE LOCKED LOOP)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the cclk
with the range of 10 MHz to 60 MHz using a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1
to 32 (in practice, the multiplier value cannot be higher than 6 on the LPC2119/2129/2292/2294 due to the upper frequency limit
of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the
CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a
50% duty cycle. A block diagram of the PLL is shown in Figure 14.
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values are controlled by the PLLCFG register.
These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since
all chip operations, including the Watchdog Timer, are dependent on the PLL when it is providing the chip clock, accidental
changes to the PLL setup could result in unexpected behavior of the microcontroller. The protection is accomplished by a feed
sequence similar to that of the Watchdog Timer. Details are provided in the description of the PLLFEED register.
The PLL is turned off and bypassed following a chip Reset and when by entering power Down mode. PLL is enabled by software
only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.
Register Description
The PLL is controlled by the registers shown in Table 21. More detailed descriptions follow.
Warning: Improper setting of PLL values may result in incorrect operation of the device.
Table 21: PLL Registers
Address Name
0xE01FC080 PLLCON
0xE01FC084 PLLCFG
0xE01FC088 PLLSTAT
0xE01FC08C PLLFEED
System Control Block
PLL Control Register. Holding register for updating PLL control bits. Values
written to this register do not take effect until a valid PLL feed sequence has taken
place.
PLL Configuration Register. Holding register for updating PLL configuration
values. Values written to this register do not take effect until a valid PLL feed
sequence has taken place.
PLL Status Register. Read-back register for PLL control and configuration
information. If PLLCON or PLLCFG have been written to, but a PLL feed
sequence has not yet occurred, they will not reflect the current PLL state.
Reading this register provides the actual values controlling the PLL, as well as the
status of the PLL.
PLL Feed Register. This register enables loading of the PLL control and
configuration information from the PLLCON and PLLCFG registers into the
shadow registers that actually affect PLL operation.
LPC2119/2129/2292/2294
Description
57
Preliminary User Manual
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January 08, 2004