Figure 46: Map Of Lower Memory After Any Reset (128 Kb Flash Part) - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller
The flash boot loader is designed to run from this memory area but both the ISP and IAP software use parts of the on-chip RAM.
The RAM usage is described later in this chapter. The interrupt vectors residing in the boot sector of the on-chip flash memory
also become active after reset i.e. the bottom 64 bytes of the boot sector are also visible in the memory region starting from the
address 0x0000 0000. The reset vector contains a jump instruction to the entry point of the flash boot loader software.
2.0 GB - 8kB
Note: memory regions are not drawn to scale.
Criterion for valid user code: The reserved ARM interrupt vector location (0x0000 0014) should contain the 2's complement of
the check-sum of the remaining interrupt vectors. This causes the checksum of all of the vectors together to be 0. The boot loader
code disables the overlaying of the interrupt vectors from the boot block, then calculates the checksum of the interrupt vectors in
sector 0 of the flash. If the signatures match then the execution control is transferred to the user code by loading the program
counter with 0x 0000 0000. Hence the user flash reset vector should contain a jump instruction to the entry point of the user
application code.
If the signature is not valid, the auto-baud routine synchronizes with the host via serial port 0. The host should send a
synchronization character('?') and wait for a response. The host side serial port settings should be 8 data bits, 1 stop bit and no
parity. The auto-baud routine measures the bit time of the received synchronization character in terms of its own frequency and
programs the baud rate generator of the serial port. It also sends an ASCII string ("Synchronized<CR><LF>") to the host. In
response to this the host should send the received string ("Synchronized<CR><LF>"). The auto-baud routine looks at the
received characters to verify synchronization. If synchronization is verified then "OK<CR><LF>" string is sent to the host. The
host should respond by sending the crystal frequency (in kHz) at which the part is running. For example if the part is running at
10 MHz a valid response from the host should be "10000<CR><LF>". "OK<CR><LF>" string is sent to the host after receiving
the crystal frequency. If synchronization is not verified then the auto-baud routine waits again for a synchronization character.
For auto-baud to work correctly, the crystal frequency should be greater than or equal to 10 MHz. The on-chip PLL is not used
by the boot code.
Once the crystal frequency is received the part is initialized and the ISP command handler is invoked. For safety reasons an
"Unlock" command is required before executing commands resulting in flash erase/write operations and the "Go" command. The
rest of the commands can be executed without the unlock command. The "Unlock" command is required to be executed once
per ISP session. Unlock command is explained in the "ISP Commands" section.
Communication Protocol
All ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line
Feed (LF) control characters. Extra <CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF> terminated
ASCII strings. Data is sent and received in UU-encoded format.
Flash Memory System and Programming
2.0 GB
(re-mapped from top of Flash memory)
(Boot Block interrupt vectors)
(8k byte Boot Block re-Mapped to higher address range)
128k byte Flash Memory
0.0 GB Active interrupt vectors from the Boot Block

Figure 46: Map of lower memory after any reset (128 kB Flash part).

8k byte Boot Block
229
Preliminary User Manual
LPC2119/2129/2292/2294
0x7FFF FFFF
0x7FFF E000
0x0001 FFFF
0x0001 E000
0x0000 0000
January 08, 2004