Technology - Samsung iDCS500 Manual

TECHNOLOGY

Memory
The system operates using stored program control. This program is stored on a SmartMedia card
inserted into the Main Control Processor card (MCP) and contains a minimum of eight Megabytes of
NAND-Flash memory. Optional, larger capacity, SmartMedia cards are also available to provide a
backup customer database and a backup operating program. The system boots from a 256 Kbyte
boot ROM and downloads the operating program into four megabytes of DRAM on the Main Control
Processor (MCP) card. The four megabytes of DRAM are increased to 8 megabytes with the addition
of the Inter Processor communications Module (IPM) in an expanded system. The customer
database is stored in 1.0 Mbytes of non-volatile SRAM for a single cabinet system. This expands to
2.5 Mbytes with the IPM installed and to 3.0 Mbytes with the addition of the optional LAN interface
module (LAN).
Microprocessors
The iDCS 500 uses distributed processing. Its primary processor is a 16 bit (32 bit core) Motorola
MC68302 operating at a clock speed of 25 MHz on the MCP card. This provides all the processing
necessary for a single cabinet system. In a multi cabinet system the secondary level of processing is
on the SCP card for the first cabinet and on the LCP cards for the expansion cabinets. These
secondary processors are MC68302 processors running at 16 MHz and provide local control of each
cabinet. Messaging between the primary and secondary processors is handled by a MC68302
processor running at 25 MHz located on the Inter Processor communications Module (IPM) PCB.
The tertiary level of processing is done in the keysets. The digital keysets use a Hitachi H8 processor
for data communication within the system.
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