Casio QT-6100 Service Manual page 59

NO. PIN NAME
219 AUDSYNC
220 AUDCK
221 VDDQ
222 VSSQ
223 AUDATA0
224 AUDATA1
225 VDD
226 VSS
227 AUDATA2
228 AUDATA3
229 Reserved
230 MD3/CE2A
231 MD4/CE2B
232 MD5
233 VDDQ
234 VSSQ
235 DACK0
236 DACK1
237 DRAK0
238 DRAK1
239 VDD
240 VSS
241 STATUS0
242 STATUS1
243 DREQ0
244 DREQ1
245 ASEBRK/BRKACK
246 TDO
247 VDDQ
248 VSSQ
249 VDD-PLL2
250 VSS-PLL2
251 VDD-PLL1
252 VSS-PLL1
253 VDD-CPG
254 VSS-CPG
255 XTAL
256 EXTAL
I: Input
O: Output
I/O: Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a
minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used.
5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D.
* I/O attribute is I/O when used as a port.
I/O
- AUD sync
- AUD clock
Power IO VDD
Power IO GND
- AUD data
Power Internal VDD
Power Internal GND
- AUD data
- Do not connect
I/O Mode/PCMCIA-CE
I/O Mode/PCMCIA-CE
I Mode MD5
Power IO VDD
Power IO GND
O DMAC0 bus acknowledge
O DMAC1 bus acknowledge
O DMAC0 request acknowledge
O DMAC1 request acknowledge
Power Internal VDD
Power Internal GND
O Status
I Request from DMAC0
I Request from DMAC1
I/O Pin break/acknowledge (H-UDI)
O Data out (H-UDI)
Power IO VDD
Power IO GND
Power PLL2 VDD
Power PLL2 GND
Power PLL1 VDD
Power PLL1 GND
Power CPG VDD
Power CPG GND
O Crystal resonator
I External input clock/crystal resonator
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DESCRIPTION