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CS-548
LINE
RECEIVER
ASSEMBLY
PAC,
MODEL
CS-548
The
Line Receiver
Assembly PAC, Model CS-548
(Figure CS-548-1), provides
14
gated outputs
used
to
receive signals
from
an l/O
bus.
CIRCUIT
FUNCTION
Signals
are received an an
l/O
bus
on
pins
2,
6,
12,
16,
20, 26,
30, 31,
17,
21, 25,
11,
3
and
7.
The
circuit
has
a built-in
terminator
for
each
signal.
Pins
8,
22,
27
and
13
provide
points for gating off-strobe signals.
SPECIFICATIONS
Input
Loading
1
unit
load
on each
input
pin
Output Drive Capacity
8
units
loads
on
pins
4,
10,
14,
18,
24,
28,
32,
29,
15,
19,
23,
9,
1
and
5
Circuit
Delay
(at
1.5V average over two
stages)
7 5
ns
Current Requirements
+
6V:
75
mA
(max)
Electrical Parts List
Ref.
Desig.
Description
CCD
Part No.
CI
CAPACITOR,
FIXED,
PLASTIC DIELECTRIC:
0.033
M-F
± 20%,
50V
70 930 313 016
Rl
thru
R14
RESISTOR, FIXED, FILM:
6.8K±
2%,
1/4W
70 932 114 069
CRl
thru
CR14
DIODE, SILICON
70 943 083 002
Ml
thru
M4
MICROCIRCUIT:
946,
quad
input
NAND
gate integrated circuit
70 950 105
002
CS-548-1
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