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SECTION
III
LOAD
MODE
TRANSFERS
Load
mode
transfers load
3-bit
characters
into the
H112
controller
for
eventual storage
in
core
as 12-bit
packed words.
Transfers occur over
the
programmed
I/O bus under HI
12
hardware
control
with no software
program
being executed.
All load
mode
transfers are
inputs
to
the controller.
Four
transfers
of
3-bit
data characters are required
to
pack each
location
(starting
location
is
determined by
the
contents
of
the
P-
register
when
function
is
initiated).
Timing
for
transfers
of
data
bits into the
Hi
12
is
controlled
by
the
transition
of
KDB09-
line
from
+6
volts
to
ground.
This strobe
signal
from
the input
device
may
have
a
period
as short as
10
fi.s
or as long as
required by
the
sending
device.
The +6V
to
ground
transition
of
KDB09-
loads
the
three least
significant
bits of the
I/O
bus
into the
three
most
significant
bits of the
accumulator.
The accumulator
is
then stored
in
the
memory
location
determined by
the
P
register.
On
the
next
KDB09-
ground-going
transition, the
following action
occurs:
a.
the
accumulator
(with the first
character)
is
right-shifted three places.
b.
the
three
least significant bits
of
the
I/O bus are loaded
into the
three
most
significant
bits of
the
accuinulator.
c.
the
accumulator
with both characters
is
stored
in
memory
at
the
location deter-
mined
by
the
P-register overwriting
the
previously stored character.
After
total of
four
characters are stored
in this
memory
location, the
P
register
is
incre-
mented
and
the
next location
is
filled.
Thus,
to
load a location with
43
2
1,
the
sequence
of
input
characters
must
be
12
3 4.
This
sequence
continues
until
a signal
is
recognized by
the
controller on
KDB07-
which
terminates
the
process.
The remainder
of the bit
configuration
included with
the
KDB07-
signal
is
ignored.
Figure
3-1
shows
the
generation
of
data characters
and
control signals
in
their
respective timing sequences.
Table
3-1
lists
the
load
mode
signal
mnemonics,
functions
and
pin
assignments.
All
the
loading
and
circuit
rules
of
the
I/O bus
apply.
Standard receiver and driver
circuits
must
be
used.
(See
Appendix
A.
)
Data
signals
need
be
stable
only during
the
KDB09-
ground-
going transition
and
3
fjis
afterward.
The
states
of
KDB06, KDB08, KDBIO, KDBll,
and
KDB12
are
not
important.
3-1
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