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INTERRUPT FLIP-FLOP
INTERRUPT SET
CONDITION,
eg.
NEW CHARACTER
INTERRUPT
RESET-
CONDITION
MASTER -
CLEAR
MSTCL-
SM
•{
MASTER
CLEAR-
SKS
AND
ADDRESS
DECODE
-I-6V
={>4k>-^-{>
SKS
DECODER
-O
KTSTL-
)-6V
-O
KINTL-
MASK
FLIP-FLOP
INTERRUPT
GENERATOR
SMK
INSTRUCTION
IMPLEMENTATION
6238
Figure
2-17.
Gating with
Mask
Flip-Flop
Interface
Example
for
Programmed
I/O Data Transfers
The
logic in
Figure 2-18
is
designed
to
transfer data
between an
external (remote)
device
and
the
HI
12
via the
programnned
l/O
bus.
The
central
processor
can
output data
at
any time
to the
device
via the output register.
Since
the
output transfer
can occur
at
any
time,
the
OTA
skip gate contains only the
device address
decode
(ADDRESS+)
and
OTA-I-
and has no
skip
term.
When
the
strobe
occurs during
OTA
15,
data
is
gated
from
the
data bus
into the
output register.
When
the
external device
sends
data
to
the interface
logic, the
data
is
presented on
the
input lines
to
the input
register.
The
data
is
loaded
when
the
external device pulses
the
line
marked
"gate data.
"
At
the
same
time,
the
"gate data"
line
sets the
"new
data
flip-
flop"
and
the
"interrupt
flip-flop.
"
Assuming
that the
mask
flip-flop
is
set,
an interrupt
is
generated.
When
the
program
interrogates
the interface
with
the
SKS
15 (skip
if
not
interrupting)
command,
the
SKS
skip gate
is
blocked and
the instruction
does
not skip.
The
controller
may
now
issue an
INA
15
which causes
an
active (ground) test signal
because
all
three
terms
into
the
INA
skip gate are
at
-1-6
volts.
The
data
from
the input
register
will
be gated
onto
the
data bus.
The new
data
flip-flop (but
not the interrupt
flip-flop) will
be reset via
the
strobe
signal.
Note
that
a
second
INA
15
issued
at this
point
will
not skip or transfer
data,
thus
new
data
from
the
device
is
transferred
into the
controller only once.
To
reset
the
2-20
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