Installation
Switch Settings
Single Throw Single pole switches are provided on the IXP/CPCI-9120 to
•
Accord Monarch status to the PrPMC
•
Force BMC or PM mode of operation for the IPMI controller
•
Disable reset of the system from the Front panel
•
Provide write-protection to BootROM Flash and User Flash
Figure 2: Location of Switches
The board is delivered with the DIP switches set to ON position for SW2 and OFF for SW3.
Table 7:
Switch settings
Switch
SW2
IXP/CPCI-9120
Position
Description
1
OFF: User Flash Write Disabled
ON: User Flash Write Enabled
2
OFF: BootROM Flash Write Disabled
ON: BootROM Flash Write Enabled
3
Reserved
Reserved
4
Reserved
Reserved
Switch Settings
49