Phy Reset Control Register; Mux Control Register - Motorola IXP-9120 Reference Manual

Figure 29: Board revision Number
Bit
3:0

PHY Reset Control Register

Address: C600 3020
Type: Read/Write
This register provides a means of controlling PHY operation. The PHY can be held in reset
until the OS is ready to initialize the PHY. This delayed reset is useful in cases where it is nec-
essary to prevent link-pulses from being sent on the line before the OS has booted (Example:
Rev C0 silicon of Marvell's 88E1145).
Table 36: PHY Reset Control Register
Bit
0

MUX Control Register

Address: C600 3040
Type: Read/Write
This register controls the flow of Ethernet signals between the RTB and PSB.
Figure 30: Mux Control Register
Bit
1:0
Description
Board Revision number for the current board
Description
0: Quad PHY Reset is asserted
1: Quad PHY Reset is de-asserted
Reset value: 0
Description
01: Port0 and Port2 of the Quad PHY are routed to RTB
Port0 and Port1 of the 82546 are routed to PSB
10: Port0 and Port2 of the Quad PHY are routed to PSB
00,11: Reserved
Reset value: 01
Access
RO
Access
R/W
Access
R/W