Table 3-3. Mpc 60X Bus To Pci Access Timing; Table 3-4. Pci To Ecc Memory Access Timing - Motorola MVME2300 Series Installation And Use Manual

Functional Description
3
Access Type
4-Beat Read (64-bit PCI Target)
4-Beat Read (32-bit PCI Target)
4-Beat Write (64-bit PCI Target)
4-Beat Write (32-bit PCI Target)
1-Beat Read (aligned, 4 bytes or
less)
1-Beat Write
Access Type
64-bit Burst Reads
64-bit Burst Writes
32-bit Burst Reads
3-6
The following table shows the access timings for various types of transfers
initiated by a 60X system bus master to PCI:

Table 3-3. MPC 60x Bus to PCI Access Timing

System Clock Periods Required For:
1st Beat
27
35
4
4
20
4
Notes 1. Write cycles are posted by the Raven ASIC.
2. Assumes no pipeline. Pipelined cycles would improve
these numbers.
3. T is assumed to be 4 system clocks (2 PCI clocks).
arb
4. T is assumed to be 6 system clocks (3 PCI clocks):
ac
Medium DEVSEL# target, zero wait PCI timing.
The following table shows the ECC memory access latency for PCI-
initiated cycles.

Table 3-4. PCI to ECC Memory Access Timing

PCI Clock Periods Required for:
1st Beat
10
3
10
2nd Beat 3rd Beat
1 1
1 1
1 1
1 1
- -
- -
2nd Beat 3rd Beat
1 1
1 1
1 1
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Total
Clocks
4th Beat
1 30
1 38
1 7
1 7
- 20
- 4
Maximum
Bandwidth
nth Beat
1
1
1