Dram Latency; Figure 4-2. Memory Block Diagram; Table 4-3. Ppc604-Bus-To-Dram Timing - 60Ns Page Devices - Motorola MVME2300SC Series Installation And Use Manual

The block diagram for the memory interface is shown in the following
figure.
Buffers

DRAM Latency

The ECC memory access latency times for 60ns, fast page DRAMs are
shown in the following table.
Table 4-3. PPC604-Bus-to-DRAM Timing — 60ns Page Devices
Access Type
4-Beat Read after Idle
(Quad-word aligned)
4-Beat Read after Idle
(Quad-word misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-7
Memory Controller
Falcon to 128M
ECC DRAM
16M to 128M
Flash
1M to 5M

Figure 4-2. Memory Block Diagram

Clock Periods Required for:
1st Beat 2nd Beat
9
9
1
7/3
General Description
Buffers
Buffers
3rd Beat 4th Beat
1 2
3 1
1 2
2390 9810
Total
Clocks
1 13
1 14
1 11/7
4