Hitachi SH7751 Hardware Manual page 623

Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit
of the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2: TEND
0
1
Bit 1—Multiprocessor Bit (MPB): This bit is read-only and cannot be written to. The read value
is undefined.
Note: This bit is prepared for storing a multi-processor bit in the received data when the receipt
is carried out with a multi-processor format in asynchronous mode, however, this does not
function correctly in this LSI. Do not use the read value from this bit.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used,
and when the operation is not transmission.
Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether
transmission has been completed before changing its value.
Bit 0: MPBT
0
1
Rev. 3.0, 04/02, page 584 of 1064
Description
Transmission is in progress
[Clearing conditions]

When 0 is written to TDRE after reading TDRE = 1

When data is written to SCTDR1 by the DMAC
Transmission has been ended
[Setting conditions]

Power-on reset, manual reset, standby mode, or module standby

When the TE bit in SCSCR1 is 0

When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit
character
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
(Initial value)
(Initial value)