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22.1.3
Pin Configuration
Table 22.1 shows the configuration of I/O pins of the PCIC.
Table 22.1 Pin Configuration
PCI
Standard
No. Pin Name
Signal
Name
1
PCICLK
CLK
2
—
3
AD31 to
AD[31:0]
AD0
4
C/
to
C/
[3:0] Command/byte
C/
5
PAR
PAR
6
7
8
9
10
11
12
/
13
/
14
15
16
17
/
MD9
Rev. 3.0, 04/02, page 804 of 1064
I/O
Function
Type
PCI input clock
in
(33 MHz/66 MHz)
Reset output
out
Address/data
t/s
t/s
enable
Parity
t/s
Bus cycle
s/t/s
Initiator ready
s/t/s
Target ready
s/t/s
Transaction stop
s/t/s
Exclusive access
s/t/s
control
Device select
s/t/s
Bus request
t/s
(host function)
Bus grant
t/s
Bus grant
t/s
(host function)
Bus request
t/s
Parity error
s/t/s
System error
o/d
Interrupt (async)
o/d
Bus request
t/s
(host function)
PCI clock switch
in
(BCLK/PCICLK)
I/O Status
in Operating Modes
Pull-up
1
Resistor*
Host
Master Target Master Target
I
O
O
I/O
I/O
O
I/O
I/O
Yes
O
Yes
O
Yes
I
O
Yes
I
O
Yes
O
Yes
I
O
Yes
I
Yes
—
—
No
O
O
No
—
—
Yes
I/O
O
Yes
O
O
Yes
—
—
Yes
I
I
Remarks
Non-host
I
I
I
—
—
I/O
I/O
Low level
output at
reset
I
O
I
Low level
output at
reset
I/O
I/O
Low level
output at
reset
I
O
I
I
O
I
I
O
I
O
I
O
I
I
O
I
—
—
I
—
—
O
I/O
O
O
O
O
O
I
—
—
I
I
I
2
*
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