Page 1 Hitachi SuperH™ RISC engine SH7750 Series SH7750, SH7750S Hardware Manual ADE-602-124C Rev. 4.0 4/21/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 Preface The SH-4 (SH7750 Series (SH7750, SH7750S)) has been developed as the top-end model in the SuperH™ RISC engine family, featuring a 128-bit graphic engine for multimedia applications and 360 MIPS performance. The SH7750 Series CPU has a RISC type instruction set, and features upward-compatibility at the object code level with SH-1, SH-2, SH-3, and SH-3E microcomputers.
Page 4 Revisions and Additions in this Edition Page Item Revisions (See Manual for Details) 1.1 SH7750 Features 167 MHz and 128 MHz operating Table 1.1 frequency versions added 5.3.1 Exception Handling Flow • R15 added to description • Save general register 15 (SGR) added to description •...
Page 5 Page Item Revision (See Manual for Details) 386 to 391 13.3.8 MPX Interface MPX interface timing conditions amended Figures 13.52 to 13.59 687, 688 22.2.2 Pin Functions (208-Pin QFP) Table amended Table 22.2 Pin Functions Pin nos. 137, 139, 141, 145 Data amended to data/port Section 23 Electronical Characteristics HD6417750BP200H,...
Page 6: Table Of Contents
Contents Section 1 Overview ......................SH7750 Series Features ....................Block Diagram ........................Section 2 Programming Model ..................Data Formats........................Register Configuration...................... 10 2.2.1 Privileged Mode and Banks ................. 10 2.2.2 General Registers ....................13 2.2.3 Floating-Point Registers..................15 2.2.4 Control Registers ....................17 2.2.5...
Page 7 3.5.2 MMU Software Management ................45 3.5.3 MMU Instruction (LDTLB)................. 45 3.5.4 Hardware ITLB Miss Handling ................46 3.5.5 Avoiding Synonym Problems ................47 MMU Exceptions......................48 3.6.1 Instruction TLB Multiple Hit Exception.............. 48 3.6.2 Instruction TLB Miss Exception................49 3.6.3 Instruction TLB Protection Violation Exception ..........
Page 8 4.5.4 OC Data Array ..................... 78 Store Queues ........................79 4.6.1 SQ Configuration....................79 4.6.2 SQ Writes......................79 4.6.3 Transfer to External Memory................79 4.6.4 SQ Protection....................... 81 Section 5 Exceptions ......................83 Overview........................... 83 5.1.1 Features........................ 83 5.1.2 Register Configuration..................83 Register Descriptions ......................
Page 9 6.6.2 Pair Single-Precision Data Transfer..............128 Section 7 Instruction Set ....................129 Execution Environment ....................129 Addressing Modes ......................131 Instruction Set ........................135 Section 8 Pipelining ......................149 Pipelines..........................149 Parallel-Executability......................156 Execution Cycles and Pipeline Stalling ................160 Section 9 Power-Down Modes ..................
Page 10 10.1.1 Features........................ 197 10.2 Overview of CPG......................199 10.2.1 Block Diagram of CPG..................199 10.2.2 CPG Pin Configuration ..................201 10.2.3 CPG Register Configuration ................201 10.3 Clock Operating Modes ....................202 10.4 CPG Register Description ....................203 10.4.1 Frequency Control Register (FRQCR)..............203 10.5 Changing the Frequency ....................
Page 11 11.2.8 Year Counter (RYRCNT) ..................225 11.2.9 Second Alarm Register (RSECAR) ..............226 11.2.10 Minute Alarm Register (RMINAR) ..............226 11.2.11 Hour Alarm Register (RHRAR) ................227 11.2.12 Day-of-Week Alarm Register (RWKAR)............227 11.2.13 Day Alarm Register (RDAYAR) ................. 228 11.2.14 Month Alarm Register (RMONAR) ..............
Page 12 13.1.1 Features........................ 257 13.1.2 Block Diagram..................... 259 13.1.3 Pin Configuration....................260 13.1.4 Register Configuration..................264 13.1.5 Overview of Areas ....................265 13.1.6 PCMCIA Support ....................268 13.2 Register Descriptions ......................272 13.2.1 Bus Control Register 1 (BCR1) ................272 13.2.2 Bus Control Register 2 (BCR2) ................280 13.2.3 Wait Control Register 1 (WCR1).................
Page 13 14.1.4 Register Configuration..................423 14.2 Register Descriptions ......................425 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......... 425 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)........426 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......427 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)........428 14.2.5 DMA Operation Register (DMAOR)..............
Page 14 15.3.3 Multiprocessor Communication Function ............543 15.3.4 Operation in Synchronous Mode ................. 551 15.4 SCI Interrupt Sources and DMAC ..................560 15.5 Usage Notes ........................561 Section 16 Serial Communication Interface with FIFO (SCIF) ......565 16.1 Overview........................... 565 16.1.1 Features........................ 565 16.1.2 Block Diagram.....................
Page 15 17.3.2 Pin Connections ....................619 17.3.3 Data Format ......................620 17.3.4 Register Settings ....................621 17.3.5 Clock........................623 17.3.6 Data Transfer Operations..................626 17.4 Usage Notes ........................633 Section 18 I/O Ports ......................639 18.1 Overview........................... 639 18.1.1 Features........................ 639 18.1.2 Block Diagrams ....................
Page 16 20.6.1 Transition to User Break Controller Stopped State..........701 20.6.2 Cancelling the User Break Controller Stopped State ........... 701 20.6.3 Examples of Stopping and Restarting the User Break Controller......702 Section 21 Hitachi User Debug Interface (H-UDI) ........... 703 21.1 Overview........................... 703 21.1.1 Features........................
Page 17 21.2.3 Bypass Register (SDBPR) ................... 708 21.3 Operation .......................... 709 21.3.1 TAP Control......................709 21.3.2 H-UDI Reset ......................710 21.3.3 H-UDI Interrupt ....................710 21.3.4 Bypass........................710 21.4 Usage Notes ........................711 Section 22 Pin Description ....................713 22.1 Pin Arrangement ....................... 713 22.2 Pin Functions ........................
Page 18: Overview
MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer). The SH7750 Series has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.
Page 19 Table 1.1 SH7750 Series Features (cont) Item Features • Original Hitachi SH architecture • 32-bit internal data bus • General register file:  Sixteen 32-bit general registers (and eight 32-bit shadow registers)  Seven 32-bit control registers  Four 32-bit system registers •...
Page 20 Table 1.1 SH7750 Series Features (cont) Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero •...
Page 21 Table 1.1 SH7750 Series Features (cont) Item Features • Clock pulse Choice of main clock: 1/2, 1, 3, or 6 times EXTAL generator (CPG) • Clock modes:  CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock: maximum 200 MHz ...
Page 22 Table 1.1 SH7750 Series Features (cont) Item Features • Cache memory Instruction cache (IC)  8 kbytes, direct mapping  256 entries, 32-byte block length  Normal mode (8-kbyte cache)  Index mode • Operand cache (OC)  16 kbytes, direct mapping ...
Page 23 Table 1.1 SH7750 Series Features (cont) Item Features • Bus state Supports external memory access controller (BSC)  64/32/16/8-bit external data bus • External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: ...
Page 24 Table 1.1 SH7750 Series Features (cont) Item Features • Serial Two full-duplex communication channels (SCI, SCIF) communication • Channel 1 (SCI): interface  Choice of asynchronous mode or synchronous mode (SCI, SCIF)  Supports smart card interface • Channel 2 (SCIF): ...
Page 25: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram of the SH7750 Series. Lower 32-bit data Lower 32-bit data I cache O cache ITLB UTLB (8 kB) (16 kB) INTC DMAC (SCIF) External bus interface 26-bit 64-bit address data BSC:...
Page 26: Programming Model
Section 2 Programming Model Data Formats The data formats handled by the SH7750 Series are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 27: Register Configuration
Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH7750 has two processor modes, user mode and privileged mode. The SH7750 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers—general registers, system registers, control registers, and floating-point registers—and the registers that can be accessed differ in the two processor modes.
Page 28: General Registers
Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0– XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX.
Page 29 R0 _ BANK0* R0 _ BANK1* R0 _ BANK0* R1 _ BANK0* R1 _ BANK1* R1 _ BANK0* R2 _ BANK0* R2 _ BANK1* R2 _ BANK0* R3 _ BANK0* R3 _ BANK1* R3 _ BANK0* R4 _ BANK0* R4 _ BANK0* R4 _ BANK1* R5 _ BANK0* R5 _ BANK0*...
Page 30 R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0– R15 in one processor mode. The SH7750 Series has two processor modes, user mode and privileged mode, in which R0–R7 are assigned as shown below.
Page 31 SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1 R3_BANK1 R4_BANK1 R4_BANK1 R5_BANK1...
Page 32: Floating-Point Registers
2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 33 • Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers XMTRX = XF0 XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10...
Page 34: Control Registers
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1 are undefined. 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 16 15 14 —...
Page 35: System Registers
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 36 Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 37: Memory-Mapped Registers
When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 38: Data Format In Registers
Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Data Format in Registers Register operands are always longwords (32 bits).
Page 39: Processor States
Little endian Figure 2.5 Data Formats In Memory Note: The SH7750 Series does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed.
Page 40 Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are two modes in the power-down state: sleep mode and standby mode. For details, see section 9, Power-Down Modes.
Page 41: Processor Modes
Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1.
Page 42: Memory Management Unit (Mmu)
(translation lookaside buffer: TLB). The SH7750 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte).
Page 43 (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in the SH7750 Series is referred to as virtual address space, and the address space in physical memory as physical address space.
Page 44 Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev. 4.0, 04/00, page 27 of 850...
Page 45: Register Configuration
3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Name tion Value* Address* Address* Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register Page table entry low PTEL Undefined H'FF00 0004 H'1F00 0004 32...
Page 46: Register Descriptions
Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4. TTB 5. TEA Virtual address at which MMU exception or address error occurred 6.
Page 47 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by hardware.
Page 48 instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software.
Page 49: Memory Space
3.3.1 Physical Memory Space The SH7750 Series supports a 32-bit physical memory space, and can access a 4-Gbyte address space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this physical memory space. The physical memory space is divided into a number of areas, as shown in figure 3.3.
Page 50: External Memory Space
P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be accessed using the cache. The P4 area is shown in detail in figure 3.4.
Page 51 H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000 Operand cache data array H'F600 0000...
Page 52 3.3.2 External Memory Space The SH7750 Series supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13, Bus State Controller (BSC).
Page 53: Virtual Memory Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1- Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256.
Page 54: On-Chip Ram Space
3.3.4 On-Chip RAM Space In the SH7750 Series, half (8 kbytes) of the instruction cache (16 kbytes) can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0 area addresses H'7C00 0000 to H'7FFF FFFF are an on-chip RAM area.
Page 55: Single Virtual Memory Mode And Multiple Virtual Memory Mode
address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed. 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either...
Page 56 Entry 0 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 1 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 2 ASID [7:0] VPN [31:10] PPN [28:10] SZ [1:0] PR [1:0] SA [2:0] Entry 63 ASID [7:0] VPN [31:10] V...
Page 57 • ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed.
Page 58 • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1.
Page 59: Instruction Tlb (Itlb) Configuration
3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type entries.
Page 60 Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match...
Page 61 Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match VPNs match...
Page 62: Mmu Functions
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, the SH7750 Series copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry.
Page 63: Hardware Itlb Miss Handling
3.5.4 Hardware ITLB Miss Handling In an instruction access, the SH7750 Series searches the ITLB. If it cannot find the necessary address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB.
Page 64: Avoiding Synonym Problems
This problem does not occur with the instruction TLB or instruction cache . In the SH7750 Series, entry specification is performed using bits [13:5] of the virtual address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4- kbyte page, are subject to address translation.
Page 65: Mmu Exceptions
MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 66: Instruction Tlb Miss Exception
3.6.2 Instruction TLB Miss Exception An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling procedure. The instruction TLB miss exception processing carried out by hardware and software is shown below.
Page 67: Instruction Tlb Protection Violation Exception
3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 68: Data Tlb Multiple Hit Exception
3.6.4 Data TLB Multiple Hit Exception A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.
Page 69: Data Tlb Protection Violation Exception
Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry.
Page 70: Initial Page Write Exception
Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 3.6.7 Initial Page Write Exception An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains...
Page 71: Memory-Mapped Tlb Configuration
Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3.
Page 72: Itlb Address Array
3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field.
Page 73: Itlb Data Array 1
3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field.
Page 74: Itlb Data Array 2
3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 75 In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether or not address comparison is performed when writing to the UTLB address array. In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits [7:0].
Page 76: Utlb Data Array 1
3.7.5 UTLB Data Array 1 UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data array are specified in the data field.
Page 77: Utlb Data Array 2
3.7.6 UTLB Data Array 2 UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field.
Page 78: Caches
4.1.1 Features The SH7750 Series has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used as on-chip RAM. The features of these caches are summarized in table 4.1.
Page 79: Register Configuration
4.1.2 Register Configuration Table 4.2 shows the cache control registers. Table 4.2 Cache Control Registers Initial Area 7 Access Name Abbreviation R/W Value* Address* Address* Size Cache control H'0000 0000 H'FF00 001C H'1F00 001C register Queue address QACR0 Undefined H'FF00 0038 H'1F00 0038 control register 0 Queue address...
Page 80 (1) Cache Control Register (CCR): CCR contains the following bits: IIX: IC index enable ICI: IC invalidation ICE: IC enable OIX: OC index enable ORA: OC RAM enable OCI: OC invalidation Copy-back enable Write-through enable OCE: OC enable Longword access to CCR can be performed from H'FF00 001C in the P4 area and H'1F00 001C in area 7.
Page 81 • OCI: OC invalidation bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always returns 0 when read. • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode •...
Page 82: Operand Cache (Oc)
Operand Cache (OC) 4.3.1 Configuration Figure 4.2 shows the configuration of the operand cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 RAM area determination [11:5] [13] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 1 bit 32 bits...
Page 83: Read Operation
The operand cache consists of 512 cache lines, each composed of a 19-bit tag, V bit, U bit, and 32- byte data. • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 84: Write Operation
3a. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 3b. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address.
Page 85 3a. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is set in the U bit. 3b.
Page 86: Write-Back Buffer
4.3.4 Write-Back Buffer In order to give priority to data reads to the cache and improve performance, the SH7750 Series has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.
Page 87: Oc Index Mode
• When OC index mode is off (CCR.OIX = 0) H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1 H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 2 H'7C00 3000 to H'7C00 3FFF (4 kB): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 4FFF (4 kB): Corresponds to RAM area 1 RAM areas 1 and 2 then repeat every 8 kbytes up to H'7FFF FFFF.
Page 88: Coherency Between Cache And External Memory
Prefetch Operation The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance.
Page 89: Instruction Cache (Ic)
Instruction Cache (IC) 4.4.1 Configuration Figure 4.5 shows the configuration of the instruction cache. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 [11:5] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 32 bits 32 bits 32 bits...
Page 90: Read Operation
The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32- byte data (16 instructions). • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset.
Page 91: Ic Index Mode
4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two 4-kbyte areas by means of effective address bit [25], providing efficient use of the cache.
Page 92: Ic Data Array
2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3.
Page 93: Oc Address Array
The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2.
Page 94 The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Page 95: Oc Data Array
4.5.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field.
Page 96: Store Queues
Store Queues The SH7750 Series supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. In the SH7750S, if the SQs are not used the low power dissipation power-down modes, in which SQ functions are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped.
Page 97 memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in the transfer to external memory is deferred until the transfer is completed. The SQ transfer destination external memory address bit [28:0] specification is as shown below, according to whether the MMU is on or off.
Page 98: Sq Protection
4.6.4 SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. If an exception occurs in an SQ write, the SQ contents may be corrupted. If an exception occurs in transfer from an SQ to external memory, the transfer to external memory will be aborted.
Page 99: Exceptions
SH7750 Series exception handling is of three kinds: for resets, general exceptions, and interrupts. 5.1.2 Register Configuration The registers used in exception handling are shown in table 5.1.
Page 100: Register Descriptions
Register Descriptions There are three registers related to exception handling. These are allocated to memory, and can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 101: Exception Handling Functions
Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 102: Exception Types And Priorities
Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset H'A000 0000 —...
Page 103 Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340...
Page 104: Exception Flow
Table 5.2 Exceptions (cont) Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral DMAC DMTE0 (VBR) H'600 H'640 type module DMTE1 H'660 interrupt DMTE2 H'680 (module/ source) DMTE3 H'6A0 DMAE H'6C0 SCIF H'700 H'720 H'740...
Page 105: Exception Source Acceptance
Reset requested? Execute next instruction Is highest- General priority exception exception requested? re-exception type? Cancel instruction execution result Interrupt requested? SSR ← SR EXPEVT ← exception code SPC ← PC SR. {MD, RB, BL, FD, IMASK} ← 11101111 SGR ← R15 PC ←...
Page 106 Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Instruction fetch ID: Instruction decode EX: Instruction execution Instruction n+3 MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously TLB miss (instruction n) Order of exception handling:...
Page 107: Exception Requests And Bl Bit
5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 108: Resets
5.6.1 Resets (1) Power-On Reset • Sources:  SCK2 pin high level and 5(6(7 pin low level  When the watchdog timer overflows while the WT/,7 bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. •...
Page 109 (2) Manual Reset • Sources:  SCK2 pin low level and 5(6(7 pin low level  When a general exception other than a user break occurs while the BL bit is set to 1 in SR  When the watchdog timer overflows while the WT/,7 bit and RSTS bit are both set to 1 in WTCSR.
Page 110 (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) • Transition address: H'A000 0000 • Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are set to B'1111.
Page 111 (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 112 (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 113: General Exceptions
5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 114 (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 115 (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 116 (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible Read/write access possible...
Page 117 (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'0000 0100 •...
Page 118 (6) Data Address Error • Sources:  Word data access from other than a word boundary (2n +1)  Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)  Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) ...
Page 119 (7) Instruction Address Error • Sources:  Instruction fetch from other than a word boundary (2n +1)  Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 120 (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 121 (9) General Illegal Instruction Exception • Sources:  Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 122 (10) Slot Illegal Instruction Exception • Sources:  Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD  Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR ...
Page 123 (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 124 (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 125 (13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 126 (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 127: Interrupts
5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H'0000 0600 • Transition operations: The contents of PC and SR immediately after the instruction at which this interrupt was accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 128 (2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 • Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC.
Page 129 (3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). •...
Page 130: Priority Order With Multiple Exceptions
5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 131: Usage Notes
Usage Notes 1. Return from exception handling a. Check the BL bit in SR with software. If SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR contents are set in SR, and branch is made to the SPC address to return from the exception handling routine.
Page 132: Restrictions
Restrictions 1. Restrictions on first instruction of exception handling routine • Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. • When the UBDE bit in the BRCR register is set to 1 and the user break debug support function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by the DBR register.
Page 133: Floating-Point Unit
A floating-point number consists of the following three fields: • Sign (s) • Exponent (e) • Fraction (f) The SH7750 Series can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 6.1 and 6.2. 23 22 Figure 6.1 Format of Single-Precision Floating-Point Number...
Page 134 52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1. The two values E –...
Page 135: Non-Numbers (Nan)
Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000 Positive denormalized...
Page 136: Denormalized Numbers
EN.V bit in the FPSCR register. An exception will not be generated in this case. The qNAN values generated by the SH7750 Series as operation results are as follows: • Single-precision qNaN: H'7FBFFFFF •...
Page 137: Registers
Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0–FR15 indicate FPR0_BANK0–FPR15_BANK0;...
Page 138 FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14 FPR15_BANK0 FR15 XF15 FPR0_BANK1...
Page 139: Floating-Point Status/Control Register (Fpscr)
6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 140: Floating-Point Communication Register (Fpul)
• Bits 22 to 31: Reserved These bits are always read as 0, and should only be written with 0. Notes: The following functions have been added to the FPU of the SH7750 Series (not provided in the FPU of the SH7718): 1.
Page 141: Floating-Point Exceptions
0, but the corresponding bit in the flag field remains unchanged. • Enable/disable exception handling The SH7750 Series supports enable exception handling and disable exception handling. Enable exception handling is initiated in the following cases:  FPU error (E): FPSCR.DN = 0 and a denormalized number is input ...
Page 142: Graphics Support Functions
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.  Inexact exception (I): An inexact result is generated. Graphics Support Functions The SH7750 Series supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 6.6.1 Geometric Operation Instructions Geometric operation instructions perform approximate-value computations.
Page 143 This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 × 4 matrix, the SH7750 Series supports 4-dimensional operations. • Matrix (4 × 4) × matrix (4 × 4): This operation requires the execution of four FTRV instructions.
Page 144: Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH7750 Series also supports high-speed data transfer instructions. When FPSCR.SZ = 1, the SH7750 Series can perform data transfer by means of pair single- precision data transfer instructions. • FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) •...
Page 145: Instruction Set
PC: At the start of instruction execution, PC indicates the address of the instruction itself. Data sizes and data types: The SH7750 Series’ instruction set is implemented with 16-bit fixed- length instructions. The SH7750 Series can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access.
Page 146 In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction execution.
Page 147: Addressing Modes
Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 148 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), Word: Rn +...
Page 149 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.
Page 150 Table 7.1 Addressing Modes and Effective Addresses (cont) Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2.
Page 151: Instruction Set
Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand →, ← Summary of Transfer direction operation...
Page 152 Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn 1001nnnndddddddd — — extension → Rn (disp × 4 + PC & H'FFFFFFFC MOV.L @(disp,PC),Rn 1101nnnndddddddd —...
Page 153 Table 7.3 Fixed-Point Transfer Instructions (cont) Instruction Operation Instruction Code Privileged T Bit R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd — — R0 → (disp × 4 + GBR) MOV.L R0,@(disp,GBR) 11000010dddddddd —...
Page 154 Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T ADDC Rm,Rn 0011nnnnmmmm1110 —...
Page 155 Table 7.4 Arithmetic Operation Instructions (cont) Instruction Operation Instruction Code Privileged T Bit EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — — byte → Rn EXTU.W Rm,Rn Rm zero-extended from 0110nnnnmmmm1101 —...
Page 156 Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...
Page 157 Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 — T → Rn → T ROTCR 0100nnnn00100101 —...
Page 158 Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd —...
Page 159 Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 — Rm → SR Rm,SR 0100mmmm00001110 Privileged Rm → GBR Rm,GBR 0100mmmm00011110 —...
Page 160 Table 7.8 System Control Instructions (cont) Instruction Operation Instruction Code Privileged T Bit 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR → Rn SR,Rn 0000nnnn00000010 Privileged — GBR →...
Page 161 Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — — (Rm) → FRn FMOV.S @Rm,FRn 1111nnnnmmmm1000 — —...
Page 162 Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF 1111nnn001011101 — — FFFF → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — When DRn = DRm, 1 → T FCMP/EQ DRm,DRn 1111nnn0mmm00100 —...
Page 163 Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn FMOV XDm,XDn 1111nnn1mmm11100 — — (Rm) → XDn FMOV @Rm,XDn 1111nnn1mmmm1000 —...
Page 164: Pipelining
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series models other than the SH7750 Series. Pipelines Figure 8.1 shows the basic pipelines.
Page 165 1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction • Address •...
Page 166 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 167 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 168 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 169 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 170 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle Notes: : Cannot overlap a stage of the same kind, except when two instructions are executed in parallel.
Page 171: Parallel-Executability
Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 172 Table 8.1 Instruction Groups (cont) 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV @(R0,Rm),DRn FNEG MOV.W @(disp,GBR),R0 FMOV @(R0,Rm),XDn FSTS FPUL,FRn MOV.W...
Page 173 Table 8.1 Instruction Groups (cont) 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV...
Page 174 Table 8.1 Instruction Groups (cont) 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L...
Page 175: Execution Cycles And Pipeline Stalling
Table 8.2 Parallel-Executability 2nd Instruction Instruction O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...
Page 176 The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 177 Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3 (g). If an executing instruction locks any resource—i.e. a function block that performs a basic operation—a following instruction that happens to attempt to use the locked resource must be stalled (figure 8.3 (h)).
Page 178 (a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction. (b) Parallel execution: parallel-executable and no dependency 1 issue cycle EX-group ADD and LS-group MOV.L can...
Page 179 (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.
Page 180 (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,R1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1 The registers are written-back in program order.
Page 181 (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2 MAC.W @R1+,@R2+ 5 stall cycles...
Page 182 Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data EXTS.B Rm,Rn — — — transfer EXTS.W Rm,Rn — — — instructions EXTU.B Rm,Rn — — — EXTU.W Rm,Rn —...
Page 183 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Data MOV.W R0,@(disp,Rn) — — — transfer MOV.L Rm,@(disp,Rn) — — — instructions MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) —...
Page 184 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4...
Page 185 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn —...
Page 186 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT —...
Page 187 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn —...
Page 188 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn —...
Page 189 Table 8.3 Execution Cycles (cont) Instruc- Execu- Lock Functional tion Issue tion Category Group Rate Pattern Stage Start Cycles Instruction Latency Double- FNEG — — — precision FSQRT (23, 24)/ floating-point instructions FSUB DRm,DRn (7, 8)/9 FTRC DRm,FPUL FPU system Rm,FPUL —...
Page 190 4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6.
Page 191: Power-Down Modes
Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: •...
Page 192 Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Conditions CPG Memory Modules Pins Memory Method Refreshing • Interrupt Sleep SLEEP Operating Halted Held Operating Held instruction (registers •...
Page 193: Register Configuration
9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Initial Area 7 Access Name Abbreviation Value P4 Address Address Size Standby control register STBCR H'00 H'FFC00004 H'1FC00004 Standby control register 2 STBCR2 H'00 H'FFC00010 H'1FC00010 9.1.3...
Page 194 Bit 7—Standby (STBY): Specifies a transition to standby mode. Bit 7: STBY Description Transition to sleep mode on execution of SLEEP instruction (Initial value) Transition to standby mode on execution of SLEEP instruction Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of peripheral module related pins in standby mode.
Page 195 Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is stopped when the MSTP3 bit is set to 1. Bit 3: MSTP3 Description SCIF operates (Initial value)
Page 196: Peripheral Module Pin High Impedance Control
9.2.2 Peripheral Module Pin High Impedance Control When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go to the high-impedance state in standby mode. • Relevant Pins SCI related pins MD0/SCK MD1/TXD2 MD7/TXD MD8/RTS2 CTS2...
Page 197: Standby Control Register 2 (Stbcr2)
9.2.4 Standby Control Register 2 (STBCR2) Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via the 5(6(7 pin or due to watchdog timer overflow. Bit: DSLP —...
Page 198: Sleep Mode
Sleep Mode 9.3.1 Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Page 199: Standby Mode
Standby Mode 9.5.1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU.
Page 200: Exit From Standby Mode
9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the 5(6(7 pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, , or on-chip peripheral module (except interval timer) interrupt is detected, the WDT starts counting.
Page 201: Module Standby Function
Module Standby Function 9.6.1 Transition to Module Standby Function Setting the MSTP4–MSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the on-chip peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.
Page 202: Status Pin Change Timing
STATUS Pin Change Timing The STATUS1 and STATUS0 pin change timing is shown below. The meaning of the STATUS pin settings is as follows: Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) The meaning of the clock units is as follows:...
Page 203: In Exit From Standby Mode
Manual Reset CKIO SCK2 Normal Reset Normal STATUS 0–30 Bcyc ≥ 0 Bcyc Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle. Figure 9.2 STATUS Output in Manual Reset 9.7.2 In Exit from Standby Mode...
Page 204 Standby → → → → Power-On Reset Oscillation stops Reset CKIO SCK2 Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When standby mode is exited by means of a power-on reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time.
Page 205: In Exit From Sleep Mode
Standby → → → → Manual Reset Oscillation stops Reset CKIO SCK2 Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold low for the PLL oscillation stabilization time.
Page 206 Sleep → → → → Power-On Reset Reset CKIO SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When sleep mode is exited by means of a power-on reset, hold low for the oscillation stabilization time. 2. Undefined Figure 9.7 STATUS Output in Sleep →...
Page 207 Sleep → → → → Manual Reset Reset CKIO SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.8 STATUS Output in Sleep → → → → Manual Reset Sequence Rev.
Page 208: In Exit From Deep Sleep Mode
9.7.4 In Exit from Deep Sleep Mode Deep Sleep → → → → Interrupt Interrupt request CKIO Sleep STATUS Normal Normal Figure 9.9 STATUS Output in Deep Sleep → → → → Interrupt Sequence Deep Sleep → → → → Power-On Reset Reset CKIO SCK2...
Page 209 Deep Sleep → → → → Manual Reset Reset CKIO SCK2 Sleep Normal Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep → → → → Manual Reset Sequence Rev.
Page 210: Section 10 Clock Oscillation Circuits
Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control. The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or the frequency is changed.
Page 211 The WDT has the following features • Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. • Can be switched between watchdog timer mode and interval timer mode •...
Page 212: Overview Of Cpg
10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figure 10.1 shows a block diagram of the CPG. Oscillator circuit Frequency divider 2 × 1 PLL circuit 1 × 1/2 × 6 × 1/3 CPU clock (Iø) × 1/4 cycle Icyc ×...
Page 213 The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6. Starting and stopping is controlled by a frequency control register setting.
Page 214: Cpg Pin Configuration
10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation Function Mode control pins Input Set clock operating mode Crystal I/O pins XTAL Output Connects crystal resonator (clock input pins) EXTAL Input Connects crystal resonator, or used as...
Page 215: Clock Operating Modes
10.3 Clock Operating Modes Table 10.3 shows the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings. Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3 Clock Operating Modes External Frequency Pin Combination (vs. Input Clock) Clock Peripheral Input Clock...
Page 216: Cpg Register Description
Table 10.4 FRQCR Settings and Internal Clock Frequencies Frequency Division Ratio Clock Ratio (I:B:P)* Peripheral 1/2 Frequency 1/2 Frequency 1/2 Frequency 1/2 Frequency FRQCR (Lower Module Divider Off Divider Off Divider On Divider On 9 Bits) Clock Clock Clock PLL1 Off PLL1 On PLL1 Off PLL1 On...
Page 217 Bit: — — — — CKOEN PLL1EN PLL2EN IFC2 Initial value: — R/W: Bit: IFC1 IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 Initial value: — — — — — — — — R/W: Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0. Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the high-impedance state.
Page 218 Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 8: IFC2 Bit 7: IFC1 Bit 6: IFC0 Description ×...
Page 219: Changing The Frequency
10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register. These methods are described below.
Page 220: Changing Bus Clock Division Ratio (When Pll Circuit 2 Is On)
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1. Make WDT settings as in 10.5.1. 2.
Page 221: Overview Of Watchdog Timer
10.7 Overview of Watchdog Timer 10.7.1 Block Diagram Figure 10.2 shows a block diagram of the WDT. Standby Standby Standby mode release control Frequency divider 2 ×1 clock Internal reset Frequency divider Reset request control Clock selection Clock selector Interrupt Interrupt Overflow request...
Page 222: Register Configuration
10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Initial Area 7 Name Abbreviation Value P4 Address Address Access Size Watchdog timer WTCNT R/W* H'00 H'FFC00008...
Page 223: Watchdog Timer Control/Status Register (Wtcsr)
10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the 5(6(7 pin. It retains its value in an internal reset due to WDT overflow.
Page 224 Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. Bit 4: WOVF Description No overflow (Initial value) WTCNT has overflowed in watchdog timer mode Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in interval timer mode.
Page 225: Notes On Register Access
10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction.
Page 226: Frequency Changing Procedure
4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. 5. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in the WTCSR register is not set at this time. 6.
Page 227: Using Interval Timer Mode
CL1 = CL2 = 0–33 pF R = 0Ω EXTAL XTAL SH7750 Series Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. Figure 10.4 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin.
Page 228 When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB, and decoupling capacitors CPB and CB, close to the pins. RCB1 VDD-PLL1 CPB1 VSS-PLL1...
Page 229: Section 11 Realtime Clock (Rtc)
Section 11 Realtime Clock (RTC) 11.1 Overview The SH7750 includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator for use by the RTC. 11.1.1 Features The RTC has the following features. • Clock and calendar functions (BCD display) Counts seconds, minutes, hours, day-of-week, days, months, and years.
Page 230: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. RTCCLK RESET, STBY, etc 16.384 kHz RTC crystal RTC operation 32.768 kHz Prescaler oscillator control unit 128 Hz RCR1 RCR2 Counter unit Interrupt R64CNT control unit RSECCNT RMINCNT RHRCNT RDAYCNT RWKCNT...
Page 231: Pin Configuration
11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation Function RTC oscillator crystal pin EXTAL2 Input Connects crystal to RTC oscillator RTC oscillator crystal pin XTAL2 Output Connects crystal to RTC oscillator Clock input/clock output TCLK External clock input pin/input capture control input pin/RTC output pin...
Page 232 Table 11.2 RTC Registers Initialization Abbrevia- Power-On Manual Standby Initial Area 7 Access Name tion Reset Reset Mode Value P4 Address Address Size Month RMONCNT R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 counter Year RYRCNT R/W Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16 counter...
Page 233: Register Descriptions
11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 234: Minute Counter (Rmincnt)
11.2.3 Minute Counter (RMINCNT) RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the second counter. The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 235: Day-Of-Week Counter (Rwkcnt)
11.2.5 Day-of-Week Counter (RWKCNT) RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 236: Day Counter (Rdaycnt)
11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter. The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set. Write processing should be performed after stopping the count with the START bit in RCR2, or by using the carry flag.
Page 237: Year Counter (Ryrcnt)
Bit: — — — 10-month 1-month units unit Initial value: Undefined Undefined Undefined Undefined Undefined R/W: 11.2.8 Year Counter (RYRCNT) RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the BCD-coded year value in the RTC. It counts on the carry generated once per year by the month counter.
Page 238: Second Alarm Register (Rsecar)
11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 239: Hour Alarm Register (Rhrar)
11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 240: Day Alarm Register (Rdayar)
Bit: — — — — Day of week Initial value: Undefined Undefined Undefined R/W: Day-of-week code Day of week 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is compared with the RDAYCNT value.
Page 241: Month Alarm Register (Rmonar)
11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC’s BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value. Comparison between the counter and the alarm register is performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
Page 242 Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.
Page 243: Rtc Control Register 2 (Rcr2)
Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF Description Alarm registers and counter values do not match (Initial value)
Page 244 Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF Interrupt is generated at interval specified by bits PES2–PES0...
Page 245 Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also reset at this time.
Page 246: Operation
11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Set RCR2.RESET to 1 Stop clock Clear RCR2.START to 0 Reset frequency divider Set second/minute/hour/day/ In any order day-of-week/month/year Set RCR2.START to 1...
Page 247: Time Reading Procedures
The procedure for setting the time while the clock is running is shown in (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data.
Page 248 Clear RCR1.CIE to 0 Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Carry flag = 1? Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Set RCR1.CIE to 1 Enable carry interrupts...
Page 249: Alarm Function
11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Be sure to reset the flag as it may have been Clear alarm flag set during alarm time setting Set RCR1.AIE to 1 Enable alarm interrupts...
Page 250: Interrupts
11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1. A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2–...
Page 251 SH7750 Series EXTAL2 XTAL2 VDD-RTC VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2. Built-in resistance value R (typ.
Page 252: Section 12 Timer Unit (Tmu)
Section 12 Timer Unit (TMU) 12.1 Overview The SH7750 includes an on-chip 32-bit timer unit (TMU) comprising three 32-bit timer channels (channels 0 to 2). 12.1.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel •...
Page 253: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. RESET, STBY, TUNI0 PCLK/4, 16, 64* TUNI1 TCLK RTCCLK TUNI2 TICPI2 etc. TCLK Prescaler control unit control unit To each To each channel channel TOCR TSTR Ch 0 Ch 1 Ch 2 Interrupt...
Page 254: Register Configuration
12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Com- Timer TOCR R/W Ini- Ini- Held H'00 H’FFD80000 H'1FD80000 8...
Page 255: Register Descriptions
12.2 Register Descriptions 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin.
Page 256: Timer Start Register (Tstr)
12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (Pφ).
Page 257: Timer Constant Registers (Tcor)
12.2.3 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are three TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value. The TCOR registers are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode.
Page 258: Timer Control Registers (Tcr)
When the input clock is the on-chip RTC output clock (RTCCLK), TCNT counts even in module standby mode (that is, when the clock for the TMU is stopped). When the input clock is the external clock (TCLK) or internal clock (Pφ), TCNT contents are retained in standby mode. 12.2.5 Timer Control Registers (TCR) The TCR registers are 16-bit readable/writable registers.
Page 259 Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit 9—Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in channel 2 only, that indicates the occurrence of input capture.
Page 260 The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished.
Page 261: Input Capture Register (Tcpr2)
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2–TPSC0): These bits select the TCNT count clock. When the on-chip RTC output clock is selected as the count clock for a channel, that channel can operate even in module standby mode. When another clock is selected, the channel does not operate in standby mode.
Page 262: Operation
12.3 Operation Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32- bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function.
Page 263 Operation selection Select count clock Underflow interrupt generation setting When input capture function is used Input capture interrupt generation setting Timer constant register setting Set initial timer counter value Start count Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.
Page 264 TCNT Count Timing: • Operating on internal clock Any of five count clocks (Pφ/4, Pφ/16, Pφ/64, Pφ/256, or Pφ/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR. Figure 12.4 shows the timing in this case.
Page 265: Input Capture Function
RTC output clock N + 1 N – 1 TCNT Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock 12.3.2 Input Capture Function Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1.
Page 266: Interrupts
TCOR value set in TCNT TCNT value on underflow TCOR H'00000000 Time TCLK TCNT value set TCPR2 TICPI2 Figure 12.7 Operation Timing when Using Input Capture Function 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used).
Page 267: Usage Notes
12.5 Usage Notes 12.5.1 Register Writes When performing a register write, timer count operation must be stopped by clearing the start bit (STR0–STR2) for the relevant channel in the timer start register (TSTR). Note that the timer start register (TSTR) can be written to, and the underflow flag (UNF) and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared while the count is in progress.
Page 268: Section 13 Bus State Controller (Bsc)
The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be connected to the SH7750 Series, and also support the PCMCIA interface protocol, enabling system design to be simplified and data transfers to be carried out at high speed by a compact system.
Page 269  Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32, 16 • Synchronous DRAM interface  Row address/column address multiplexing according to synchronous DRAM capacity  Burst operation  Auto-refresh and self-refresh  Synchronous DRAM control signal timing can be controlled by register settings ...
Page 270: Block Diagram
13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. interface WCR1 Wait control unit WCR2 WCR3 Area – BCR1 control unit – BCR2 – Memory control unit RFCR RTCNT Refresh Interrupt Comparator control unit controller RTCOR RTCSR WCR: Wait control register RFCR: Refresh count register...
Page 271: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals Description Address bus A25–A0 Address output Data bus D63–D52, Data input/output D31–D0 When port functions are used and DDT mode is selected, input the DTR format. Otherwise, when port functions are used, D60-D52 cannot be used and should be left open.
Page 272 Table 13.1 BSC Pins (cont) Name Signals Description :(4/&$64/ Data enable 1 When setting synchronous DRAM interface: DQM1 selection signal for D15–D8 When setting DRAM interface: &$6 signal for D15–D8 When setting PCMCIA interface: write strobe signal When setting MPX interface: high-level output In other cases: write strobe signal for D15–D8 :(5/&$65/ Data enable 2...
Page 273 Table 13.1 BSC Pins (cont) Name Signals Description :(9/&$69/ Data enable 6 When setting synchronous DRAM interface: DQM6 selection signal for D55–D48 When setting DRAM interface: &$6 signal for D55–D48 When setting MPX interface: high-level output In other cases: write strobe signal for D55–D48 :(:/&$6:/ Data enable 7 When setting synchronous DRAM interface:...
Page 274 Table 13.1 BSC Pins (cont) Name Signals Description Same signal as 5'/&$66/)5$0( Read/column address strobe/ This signal is used when the 5'/&$66/)5$0( cycle frame 2 signal load is heavy. Read/write 2 RD/:55 Same signal as RD/:5 This signal is used when the RD/:5 signal load is heavy.
Page 275: Register Configuration
The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as an SH7750 Series register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing.
Page 276: Overview Of Areas
With the SH7750 Series, various kinds of memory or PC cards can be connected to the seven areas of external address as shown in table 13.3, and chip select signals (&63–&69, &(5$, &(5%) are output for each of these areas.
Page 277 Table 13.3 External Memory Space Map External Connectable Settable Bus Area Addresses Size Memory Widths Access Size H'00000000– 64 Mbytes SRAM 8, 16, 32, 64* 8, 16, 32, H'03FFFFFF bits, Burst ROM 8, 16, 32* 32 bytes 32, 64* H'04000000– 64 Mbytes SRAM 8, 16, 32, 64*...
Page 278 Figure 13.3 External Memory Space Allocation Memory Bus Width: In the SH7750 Series, the memory bus width can be set independently for each space. For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset, using external pins.
Page 279: Pcmcia Support
The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used. 13.1.6 PCMCIA Support The SH7750 Series supports PCMCIA compliant interface specifications for external memory space areas 5 and 6. The interfaces supported are the IC memory card interface and I/O card interface stipulated in JEIDA specifications version 4.2 (PCMCIA2.1).
Page 280 Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Ground Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...
Page 281 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data ,2,649 ,2,649...
Page 282 Table 13.5 PCMCIA Support Interfaces (cont) IC Memory Card Interface I/O Card Interface Corresponding Signal Signal SH7750 Series Name I/O Function Name I/O Function Reserved Reserved — RESET Reset RESET Reset Output from port :$,7 :$,7 5'< Wait request Wait request ,13$&.
Page 283: Register Descriptions
13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 284 Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset. The endian mode of all spaces is determined by this bit. ENDIAN is a read-only bit. Bit 31: ENDIAN Description In a power-on reset, the endian setting external pin (MD5) is low, designating big-endian mode for the SH7750 In a power-on reset, the endian setting external pin (MD5) is high, designating little-endian mode for the SH7750...
Page 285 Bit 25—Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor status for control input pins (NMI, ,5/3–,5/6, %5(4, MD6/,2,649, 5'<). IPUP is initialized by a power-on reset. Bit 25: IPUP Description Pull-up resistor is on for control input pins (NMI, ,5/3–,5/6, %5(4, MD6/,2,649, 5'<) (Initial value) Pull-up resistor is off for control input pins (NMI, ,5/3–,5/6, %5(4,...
Page 286 Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted. BREQEN is initialized to the external request acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup. Bit 19: BREQEN Description External requests are not accepted (Initial value) External requests are accepted...
Page 287 Bit 14—High Impedance Control (HIZCNT): Specifies the state of the 5$6 and &$6 signals in standby mode and when the bus is released. Bit 14: HIZCNT Description The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals go to high-impedance (High-Z) in standby mode and when the bus is released (Initial value) The 5$6, 5$65, :(Q/&$6Q/DQMn, 5'/&$66/)5$0(, and 5'5 signals...
Page 288 Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0...
Page 289 Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0...
Page 290 Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description Areas 2 and 3 are SRAM interface or MPX interface*...
Page 291: Bus Control Register 2 (Bcr2)
13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 292: Wait Control Register 1 (Wcr1)
In the SH7750 Series, the number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of this kind of data bus collision.
Page 293 Bit: Bit name: — DMAIW2 DMAIW1 DMAIW0 — A6IW2 A6IW1 A6IW0 Initial value: R/W: Bit: Bit name: — A5IW2 A5IW1 A5IW0 — A4IW2 A4IW1 A4IW0 Initial value: R/W: Bit: Bit name: — A3IW2 A3IW1 A3IW0 — A2IW2 A2IW1 A2IW0 Initial value: R/W: Bit: Bit name:...
Page 294: Wait Control Register 2 (Wcr2)
DMAIW2/AnIW2 DMAIW1/AnIW1 DMAIW0/AnIW0 Inserted Idle Cycles (Initial value) • Idle Insertion between Accesses Following Cycle Same Different Same Area Different Area Area Area Read Write Read Write Preceding Address Address Cycle CPU DMA CPU DMA CPU DMA CPU DMA Output Output Read M (1)
Page 295 WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset or in standby mode. Bit: Bit name: A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 Initial value: R/W: Bit: Bit name: A5W0 A5B2 A5B1 A5B0 A4W2...
Page 296 Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from Second Data 5'<...
Page 297 Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to be inserted from the second data access onward in a burst transfer. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from 5'< Pin 5'<...
Page 298 Bits 15 to 13—Area 3 Wait Control (A3W2–A3W0): These bits specify the number of wait states to be inserted for area 3. External wait input is only enabled when SRAM interface is used, and is ignored when DRAM or synchronous DRAM is used. •...
Page 299 Bits 11 to 9—Area 2 Wait Control (A2W2–A2W0): These bits specify the number of wait states to be inserted for area 2. External wait input is only enabled when normal memory is used, and is ignored when DRAM or synchronous DRAM is used. •...
Page 300 Bits 8 to 6—Area 1 Wait Control (A1W2–A1W0): These bits specify the number of wait states to be inserted for area 1. Description 5'< 5'< Pin 5'< 5'< Bit 8: A1W2 Bit 7: A1W1 Bit 6: A1W0 Inserted Wait States Ignored Enabled Enabled...
Page 301 Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the burst pitch to in burst ROM interface setting. Description Burst Cycle (Excluding First Cycle) Wait States Inserted from 5'< Pin 5'< 5'< 5'< Bit 2: A0B2 Bit 1: A0B1 Bit 0: A0B0 Second Data Access Onward Ignored...
Page 302: Wait Control Register 3 (Wcr3)
13.2.5 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area. This enables low-speed memory to be connected without using external circuitry.
Page 303: Memory Control Register (Mcr)
Valid only for SRAM interface and burst ROM interface: Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Bit 4n + 2: AnS0 Waits Inserted in Setup (Initial value)
Page 304 Bit: Bit name: RASD MRSET TRC2 TRC1 TRC0 — — — Initial value: R/W: Bit: Bit name: TCAS — TPC2 TPC1 TPC0 — RCD1 RCD0 Initial value: R/W: Bit: Bit name: TRWL2 TRWL1 TRWL0 TRAS2 TRAS1 TRAS0 Initial value: R/W: Bit: Bit name: AMXEXT AMX2...
Page 305 Bits 29 to 27—RAS Precharge Time at End of Refresh (TRC2–TRC0) (Synchronous DRAM: auto- and self-refresh both enabled; DRAM: auto- and self-refresh both enabled) RAS Precharge Interval Bit 29: TRC2 Bit 28: TRC1 Bit 27: TRC0 Immediately after Refresh (Initial value) Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written with 0.
Page 306 RAS Precharge Interval Bit 21: TPC2 Bit 20: TPC1 Bit 19: TPC0 DRAM Synchronous DRAM 1* (Initial value) Note: * Inhibited in RAS down mode. Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits set the 5$6-&$6 assertion delay time.
Page 307 Bit 15: TRWL2 Bit 14: TRWL1 Bit 13: TRWL0 Write Precharge ACT Delay Time 1 (Initial value) Reserved (Setting prohibited) Reserved (Setting prohibited) Reserved (Setting prohibited) Note: * Inhibited in RAS down mode. Bits 12 to 10—CAS-Before-RAS Refresh 5$6 5$6 Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the 5$6 assertion period in CAS-before-RAS refreshing.
Page 308 EDOMODE 8/16/32/64-Bit Transfer 32-Byte Transfer Single Single Setting prohibited Setting prohibited Single/fast page* Fast page Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus. Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM.
Page 309 (16M: 256k × 32 bits × 2) × 1 a[20]* Notes: 1. a[*]: External address 2. Setting prohibited in the SH7750 Series. 3. Setting prohibited in the SH7750. 4. Can only be set in the SH7750S. Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is performed for DRAM and synchronous DRAM.
Page 310: Pcmcia Control Register (Pcr)
Bit 1—Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS- before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR.
Page 311 Bits 15 and 14—PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA access TC bit is cleared to 0. Bit 15: A5PCW1 Bit 14: A5PCW0 Waits Inserted...
Page 312 2(/:( :( Assertion Delay (A6TED2–A6TED0): These bits set the delay Bits 8 to 6—Address-2( time from address output to 2(/:( assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA access TC bit is set to 1. Bit 8: A6TED2 Bit 7: A6TED1 Bit 6: A6TED0...
Page 313: Synchronous Dram Mode Register (Sdmr)
DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of the SH7750 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7750 Rev. 4.0, 04/00, page 302 of 850...
Page 314 Series, the value actually written to the synchronous DRAM is the value of “X” shifted 2 bits to the right. For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address H'FF900000 (address “Y”) + H'08C0 (value “X”) (= H'FF9008C0). As a result, H'0230 is written to the SDMR register.
Page 315: Refresh Timer Control/Status Register (Rtscr)
13.2.9 Refresh Timer Control/Status Register (RTSCR) The refresh timer control/status register (RTSCR) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated. RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 316 Bits 5 to 3—Clock Select Bits (CKS2–CKS0): These bits select the input clock for RTCNT. The base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO by the specified factor. Bit 5: CKS2 Bit 4: CKS1 Bit 3: CKS0 Description...
Page 317: Refresh Timer Counter (Rtcnt)
Bit 0—Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value exceeds the value specified by LMTS, the OVF flag is set. Bit 0: LMTS Description Count limit is 1024...
Page 318: Refresh Count Register (Rfcr)
RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in a manual reset and in standby mode. Bit: Bit name: — — — — — — — — Initial value: R/W: — —...
Page 319: 13.2.13 Notes On Accessing Refresh Control Registers
13.2.13 Notes on Accessing Refresh Control Registers When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The following procedures should be used for read/write operations.
Page 320: Operation
13.3.1 Endian/Access Size and Data Alignment The SH7750 Series supports both big-endian mode, in which the most significant byte (MSByte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (LSByte) is at the 0 address end.
Page 321 Table 13.6 (1) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte Data — — — — — — — 7–0 8n+1 — Data — — —...
Page 322 Table 13.6 (2) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Strobe Signals :(:, :(9, :(8, :(7, :(6, :(5, :(4, :(3, &$6:, &$6: &$69 &$69, &$68, &$68 &$67 &$67, &$66, &$66 &$65, &$65 &$64 &$64, &$63 &$63, &$6: &$6: &$69 &$69 &$68 &$68...
Page 323 Table 13.7 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66, &$66 &$65 &$65, &$64 &$64, &$63 &$63, &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 324 Table 13.8 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66 &$66, &$65, &$65 &$64, &$64 &$63, &$63 &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 325 Table 13.9 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66, &$66 &$65 &$65, &$64 &$64, &$63 &$63, &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 326 Table 13.10 (1) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte — — — — — — — Data 7–0 8n+1 — — — — —...
Page 327 Table 13.10 (2) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Strobe Signals :(:, :(9, :(8, :(7, :(6, :(5, :(4, :(3, &$6: &$6:, &$69, &$69 &$68 &$68, &$67, &$67 &$66, &$66 &$65 &$65, &$64, &$64 &$63, &$63 &$6: &$6: &$69 &$69 &$68 &$68...
Page 328 Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66, &$66 &$65 &$65, &$64 &$64, &$63 &$63, &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3...
Page 329 Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66 &$66, &$65, &$65 &$64 &$64, &$63, &$63 &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 330 Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals :(6, :(5, :(4, :(3, &$66 &$66, &$65, &$65 &$64, &$64 &$63, &$63 &$66 &$66 &$65 &$65 &$64 &$64 &$63 &$63 Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1...
Page 331: Areas
13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins MD4 and MD3.
Page 332 interface is set, select 32 or 64 bits with the SZ bits in the MCR register. When DRAM is connected to area 2, select a bus width of 16 or 32 bits with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5.
Page 333 The read/write strobe signal address and &6 setup and hold times can be set within a range of 0–1 and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3 register. When synchronous DRAM interface is set, the 5$6 and &$6 signals, RD/:5 signal, and byte control signals DQM0 to DQM7 are asserted, and address multiplexing is performed.
Page 334 as 2(, and the :(4, :(5, :(6, and :(: signals, which can be used as :(, ,&,25', ,&,2:5, and 5(*, respectively, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0 in the WCR2 register.
Page 335: Basic Interface
13.3.3 Basic Interface Basic Timing: The basic interface of the SH7750 Series uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.5 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The %6 signal is asserted for one cycle to indicate the start of a bus cycle.
Page 336 CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Single address DMA Dual address DMA Figure 13.5 Basic Timing of Basic Interface Rev. 4.0, 04/00, page 325 of 850...
Page 337 Figures 13.6, 13.7, 13.8, and 13.9 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM. × 128K 8-bit SH7750 Series SRAM A19–A3 A16–A0 D63–D56 I/O7–I/O0 A16–A0 D55–D48 I/O7–I/O0 A16–A0 D47–D40 I/O7–I/O0 A16–A0 D39–D32 I/O7–I/O0 A16–A0 D31–D24 I/O7–I/O0...
Page 338 128K × 8-bit SH7750 Series SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 13.7 Example of 32-Bit Data Width SRAM Connection Rev. 4.0, 04/00, page 327 of 850...
Page 339 128K × 8-bit SH7750 Series SRAM I/O7 I/O0 I/O7 I/O0 Figure 13.8 Example of 16-Bit Data Width SRAM Connection Rev. 4.0, 04/00, page 328 of 850...
Page 340 128K × 8-bit SH7750 Series SRAM I/O7 I/O0 Figure 13.9 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification.
Page 341 CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Figure 13.10 Basic Interface Wait Timing (Software Wait Only) Rev. 4.0, 04/00, page 330 of 850...
Page 342 When software wait insertion is specified by WCR2, the external wait input 5'< signal is also sampled. 5'< signal sampling is shown in figure 13.11. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the 5'<...
Page 343: Dram Interface
13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect DRAM to the SH7750. 16, 32, or 64 bits can be selected as the interface data width for area 3 when bits DRAMTP2–0 are set to 100, and 16 or 32 bits can be used for both area 2 and area 3 when bits DRAMTP2–0 are set to 101.
Page 344 1M × 16-bit SH7750 Series DRAM A12–A3 A9–A0 I/O15–I/O0 D63–D48 A9–A0 D47–D32 I/O15–I/O0 A9–A0 D31–D16 I/O15–I/O0 A9–A0 D15–D0 I/O15–I/O0 Figure 13.12 Example of DRAM Connection (64-Bit Data Width, Area 3) Rev. 4.0, 04/00, page 333 of 850...
Page 345 256K × 16-bit SH7750 Series DRAM I/O15 I/O0 I/O15 I/O0 Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev. 4.0, 04/00, page 334 of 850...
Page 346 256K × 16-bit SH7750 Series DRAM Area 3 I/O15 I/O0 Area 2 I/O15 I/O0 Figure 13.14 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) Rev. 4.0, 04/00, page 335 of 850...
Page 347 DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to the SH7750 Series without using an external address multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting bits AMXEXT and AMX2–0 in MCR for area 2 or 3 DRAM.
Page 348 Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.15. Tpc is the precharge cycle, Tr the 5$6 assert cycle, Tc1 the &$6 assert cycle, and Tc2 the read data latch cycle. CKIO A25–A0 Column...
Page 349 Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.16.
Page 350 Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. This mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access.
Page 351 EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the &$6 signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the &$6 signal is asserted while the 5$6 signal is asserted, even if the &$6 signal is negated, data is output to the data bus until the &$6 signal is next asserted.
Page 352 (SA: IO ← memory) Figure 13.19 Burst Access Timing in DRAM EDO Mode RAS Down Mode: The SH7750 Series has an address comparator for detecting row address matches in burst mode. By using this address comparator, and also setting RAS down mode specification bit RASD to 1, it is possible to select RAS down mode, in which 5$6 remains asserted after the end of an access.
Page 353 CKIO A25–A0 D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Figure 13.20 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, Anw = 0) Rev. 4.0, 04/00, page 342 of 850...
Page 354 Tnop CKIO A25–A0 End of RAS down mode D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Figure 13.20 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, Anw = 0) Rev.
Page 355 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.20 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, Anw = 0) Rev. 4.0, 04/00, page 344 of 850...
Page 356 CKIO A25–A0 End of RAS down mode D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.20 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, Anw = 0) Rev. 4.0, 04/00, page 345 of 850...
Page 357 RTCOR value, and if the two values are the same, a refresh request is generated and the %$&. pin goes high. If the SH7750 Series’ external bus can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted.
Page 358 Figure 13.22 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) • Self-Refresh The self-refreshing supported by the SH7750 Series is shown in figure 13.23. After the self-refresh is cleared, the refresh controller immediately generates a refresh request.
Page 359 1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g. 1024 cycles/128 ms). 2. When a transition is made to self-refreshing: a. Provide an interrupt handler to restore the refresh counter count value to the optimum value for the L version (e.g.
Page 360 SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series. TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 D63–D0 Figure 13.23 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 µs or 200 µs) during which no access can be performed be provided, followed by at...
Page 361: Synchronous Dram Interface
DRAM space. With the SH7750 Series, burst read/burst write mode is supported as the synchronous DRAM operating mode. The data bus width is 32 or 64 bits, and the SZ size bits in MCR must be set to 00 or 11.
Page 362 512K × 16-bit × 2-bank SH7750 Series synchronous DRAM A12–A3 A9–A0 CKIO D63–D48 I/O15–I/O0 DQM7 DQMU DQM6 DQML A9–A0 I/O15–I/O0 D47–D32 DQMU DQM5 DQML DQM4 A9–A0 D31–D16 I/O15–I/O0 DQM3 DQMU DQM2 DQML A9–A0 D15–D0 I/O15–I/O0 DQM1 DQMU DQM0 DQML Figure 13.24 Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3)
Page 363 The address signals output at A25–A18, A1, and A0 are undefined. When A0, the LSB of the synchronous DRAM address, is connected to the SH7750 Series, with a 32-bit bus width it makes a longword address specification. Connection should therefore be made in this order: connect pin A0 of the synchronous DRAM to pin A2 of the SH7750, then connect pin A1 to pin A3.
Page 364 DRAM; no new access command can be issued to the same bank during this cycle. In the SH7750 Series, the number of Tpc cycles is determined by the specification of bits TPC2– TPC0 in MCR, and commands are not issued for the same synchronous DRAM during this interval.
Page 365 independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.26 Basic Timing for Synchronous DRAM Burst Read In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the start of the data transfer cycle corresponding to the READ or READA command.
Page 366 To prevent data collisions, after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the SH7750 Series waits for the end of the synchronous DRAM operation. The %6 signal is asserted only in Td1.
Page 367 Burst Write: The timing chart for a burst write is shown in figure 13.28. In the SH7750, a burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write operation, the WRIT command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and, 4 cycles later, the WRITA command is issued.
Page 368 Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. As the SH7750 Series supports burst read/burst write operations for synchronous DRAM, there are empty cycles in a single write operation.
Page 369 Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Figure 13.29 Basic Timing for Synchronous DRAM Single Write Rev. 4.0, 04/00, page 358 of 850...
Page 370 RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 371 that in figure 13.31 or 13.34. In RAS down mode, too, a PRE command is issued before a refresh cycle or before bus release due to bus arbitration. Tc3 Tc4/Td1 Td2 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.30 Burst Read Timing Rev.
Page 372 Tc3 Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.31 Burst Read Timing (RAS Down, Same Row Address) Rev. 4.0, 04/00, page 361 of 850...
Page 373 Tc4/Td1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO ← memory) Figure 13.32 Burst Read Timing (RAS Down, Different Row Addresses) Rev. 4.0, 04/00, page 362 of 850...
Page 374 Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Figure 13.33 Burst Write Timing Rev. 4.0, 04/00, page 363 of 850...
Page 375 Tncp* Tnop* Trw1 Trw1 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Notes: 1. Tncp: DACK output start cycle (inserted only in the case of DACK output) 2. Tnop: Dummy cycle (always inserted) Figure 13.34 Burst Write Timing (Same Row Address) Rev.
Page 376 CKIO Bank Precharge-sel Address DQMn D63–D0 (read) DACKn (SA: IO → memory) Figure 13.35 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM.
Page 377 addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACT command, depending on the bank and row address, but since the write data is output at the same time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that one or two empty cycles occur automatically on the data bus.
Page 378 Tc1_A Tc1_B CKIO Bank Precharge-sel Address DQMn D63–D0 (read) Figure 13.36 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Refreshing: The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR.
Page 379 First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by bits TRAS2–TRAS0 in MCR plus the number of cycles specified by bits TRC2–TRC0 in MCR. The TRAS2– TRAS0 and TRC2–TRC0 bits must be set so as to satisfy the synchronous DRAM refresh cycle time specification (active/active command delay time).
Page 380 TRr1 TRr2 TRr3 TRr4 TRrw TRr5 CKIO DQMn D63–D0 Figure 13.38 Synchronous DRAM Auto-Refresh Timing • Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1.
Page 381 When a refresh request is generated, the %$&. pin is negated (driven high). Therefore, normal refreshing can be performed by having the %$&. pin monitored by a bus master other than the SH7750 Series requesting the bus, or the bus arbiter, and returning the bus to the SH7750 Series.
Page 382 Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the 5$6, &$6, and RD/:5 signals.
Page 383 Synchronous DRAM mode register setting should be executed once only after power-on and before synchronous DRAM access, and no subsequent changes should be made. TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.40 (1) Synchronous DRAM Mode Write Timing Rev.
Page 384 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address D31–D0 (High) Figure 13.40 (2) Synchronous DRAM Mode Write Timing Rev. 4.0, 04/00, page 373 of 850...
Page 385: Burst Rom Interface
13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a non- zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.41.
Page 386 CKIO A25–A5 A4–A0 D63–D0 (read) DACKn (SA: IO ← memory) Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 13.41 Burst ROM Basic Access Timing Rev. 4.0, 04/00, page 375 of 850...
Page 387 CKIO A25–A5 A4–A0 D63–D0 (read) DACKn (SA: IO ← memory) Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 13.42 Burst ROM Wait Access Timing Rev. 4.0, 04/00, page 376 of 850...
Page 388: Pcmcia Interface
13.3.7 PCMCIA Interface In the SH7750 Series (SH7750 and SH7750S), setting the A56PCM bit in BCR1 to 1 makes the bus interface for external space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1).
Page 389 to A6TEH0 in the PCMCIA control register (PCR), are selected. For the method of setting bits SA2 to SA0 and bit TC, see the MMU section. In the SH7750S, the PCMCIA interface can be accessed even when the MMU is not used. When the MMU is off, access is always performed by means of bits SA2 to SA0 and bit TC in the page table entry assistance register (PTEA).
Page 390 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Read Even Don’t — Invalid Read data care Don’t — Invalid Read data care Even Don’t...
Page 391 Table 13.17 Relationship between Address and CE When Using PCMCIA Interface (cont) Access Width Read/ Size Odd/ (Bits) Write (Bits)* Even IOIS16 Access CE2 CE1 A0 D15–D8 D7–D0 Dynamic Read Even — Invalid Read data — Read data Invalid sizing* Even —...
Page 392 A25–A0 A25–A0 D15–D0 D7–D0 D15–D0 PC card D15–D8 (memory I/O) SH7750 Series Card detection CD1, CD2 circuit Output A25–A0 Port D7–D0 D15–D0 D15–D8 PC card (memory I/O) Card CD1, CD2 detection circuit Figure 13.44 Example of PCMCIA Interface Rev. 4.0, 04/00, page 381 of 850...
Page 393 Memory Card Interface Basic Timing: Figure 13.45 shows the basic timing for the PCMCIA IC memory card interface, and figure 13.46 shows the PCMCIA memory bus wait timing. Tpcm1 Tpcm2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.45 Basic Timing for PCMCIA Memory Card Interface Rev.
Page 394 Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.46 Wait Timing for PCMCIA Memory Card Interface Rev. 4.0, 04/00, page 383 of 850...
Page 395 Common memory (64 MB) Physical Access address space by CS5 wait Physical I/O controller addresses 1 kB IO 1 Virtual Access page address space by CS6 wait IO 1 controller Common IO 2 memory 1 Card 1 Common memory 2 on CS5 IO 2 Attribute memory...
Page 396 Tpci1 Tpci2 CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.48 Basic Timing for PCMCIA I/O Card Interface Rev. 4.0, 04/00, page 385 of 850...
Page 397 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Figure 13.49 Wait Timing for PCMCIA I/O Card Interface Rev. 4.0, 04/00, page 386 of 850...
Page 398 Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w CKIO A25–A1 CExx REG (WE7) RD/WR IORD (WE2) (read) D15–D0 (read) IOWR (WE3) (write) D15–D0 (write) IOIS16 DACKn (DA) Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.
Page 399: Mpx Interface
Access Size Byte Word Longword Quadword 32-byte burst X: Don’t care SH7750 Series MPX device CKIO D63–D0 I/O63–I/O0 Figure 13.51 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in BCR2.
Page 400 For wait control, waits specified by WCR2 and wait insertion by means of the 5'< pin can be used. In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to Tmd1w Tmd1 CKIO D63–D0 DACKn (DA)
Page 401 Tmd1w Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) Rev. 4.0, 04/00, page 390 of 850...
Page 402 Tmd1 CKIO D63–D0 DACKn (DA) Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) Rev. 4.0, 04/00, page 391 of 850...
Page 403 Tmd1w Tmd1w Tmd1 CKIO D63–D0 DACKn (DA) Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) Rev. 4.0, 04/00, page 392 of 850...
Page 404 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 393 of 850...
Page 405 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 394 of 850...
Page 406 Tmd1 Tmd2 Tmd3 Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 395 of 850...
Page 407 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO D63–D0 DACKn (DA) Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 396 of 850...
Page 408 Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.60 MPX Interface Timing 1 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 397 of 850...
Page 409 Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.61 MPX Interface Timing 2 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 398 of 850...
Page 410 Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.62 MPX Interface Timing 3 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 399 of 850...
Page 411 Tmd1w Tmd1w Tmd1 Tmd2 CKIO D31–D0 DACKn (DA) Figure 13.63 MPX Interface Timing 4 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bytes) Rev. 4.0, 04/00, page 400 of 850...
Page 412 Figure 13.64 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 401 of 850...
Page 413 Figure 13.65 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 402 of 850...
Page 414 Figure 13.66 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 403 of 850...
Page 415 Figure 13.67 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev. 4.0, 04/00, page 404 of 850...
Page 416: Byte Control Sram
13.3.9 Byte Control SRAM The byte control SRAM interface is a memory interface that outputs a byte select strobe (:(Q) in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB.
Page 417 64K × 16-bit SH7750 Series SRAM A18–A3 A15–A0 I/O15–I/O0 D63–D48 A15–A0 D47–D32 I/O15–I/O0 A15–A0 D31–D16 I/O15–I/O0 A15–A0 D15–D0 I/O15–I/O0 Figure 13.68 Example of 64-Bit Data Width Byte Control SRAM Rev. 4.0, 04/00, page 406 of 850...
Page 418 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait) Rev. 4.0, 04/00, page 407 of 850...
Page 419 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev. 4.0, 04/00, page 408 of 850...
Page 420 CKIO A25–A0 D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev. 4.0, 04/00, page 409 of 850...
Page 421: 13.3.10 Waits Between Access Cycles
13.2.3, Wait Control Register (WCR1). When the SH7750 Series performs consecutive write cycles, the data transfer direction is fixed (from the SH7750 Series to other memory) and there is no problem. With read accesses to the same area, also, in principle data is output from the same data buffer, and wait cycle insertion is not performed.
Page 422: 13.3.11 Bus Arbitration
Figure 13.72 Waits between Access Cycles 13.3.11 Bus Arbitration The SH7750 Series is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. Also provided is a bus arbitration function to support the connection of two processors.
Page 423 Bus transfer is executed between bus cycles. When the bus release request signal (%5(4) is asserted, the SH7750 Series releases the bus as soon as the currently executing bus cycle ends, and outputs the bus use permission signal (%$&.).
Page 424 As the CPU in the SH7750 Series is connected to cache memory by a dedicated internal bus, reading from cache memory can still be carried out when the bus is being used by another bus master inside or outside the SH7750 Series. When writing from the CPU, an external write cycle is generated when write-through has been set for the cache in the SH7750 Series, or when an access is made to a cache-off area.
Page 425 CKIO Asserted for at least 2 cyc Negated within 2 cyc A25–A0 D63–D0 (write) Master mode device access Must be asserted for Must be negated within 2 cyc at least 2 cyc A25–A0 D63–D0 (write) Slave mode device access Master access Slave access Master access Figure 13.73 Arbitration Sequence...
Page 426: 13.3.12 Master Mode
%$&. signal is negated even while the %5(4 signal is asserted to request the slave to relinquish the bus. When the SH7750 Series is used in master mode, consecutive bus accesses may be attempted to reduce the overhead due to arbitration in the case of a slave designed independently...
Page 427: 13.3.13 Slave Mode
by the user. When connecting a slave for which the total duration of consecutive accesses exceeds the refresh cycle, the design should provide for the bus to be released as soon as possible after negation of the %$&. signal is detected. 13.3.13 Slave Mode In slave mode, the bus is normally in the released state, and an external device cannot be accessed unless the bus is acquired through execution of the bus arbitration sequence.
Page 428 Partial-sharing master mode is designed for use in conjunction with a master mode chip. The partial-sharing master can access a device on the master side via area 2, but the master cannot access a device on the partial-sharing master side. An address and control signal buffer and a data buffer must be located between the partial-sharing master and the master, and controlled by a buffer control circuit.
Page 429: 13.3.15 Cooperation Between Master And Slave
2, while the master performs initialization of the memory connected to it. If the SH7750 Series is specified as the master in a power-on reset, it will not accept bus requests from the slave until the %5(4 enable bit (BCR1.BREQEN) is set to 1.
Page 430: Section 14 Direct Memory Access Controller (Dmac)
14.1 Overview The SH7750 Series includes an on-chip four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (DMA transfer end notification), external memories, memory- mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC).
Page 431 • Choice of bus mode: Cycle steal mode or burst mode • Two types of DMAC channel priority ranking:  Fixed priority mode: Channel priorities are permanently fixed.  Round robin mode: Sets the lowest priority for the channel for which an execution request was last accepted.
Page 432: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of the DMAC. DMAC module Count SARn control Register DARn control DMATCRn Activation On-chip control peripheral CHCRn module DMAOR Request priority SCI, SCIF control DACK0, DACK1 DRAK0, DRAK1 interface SAR0, DAR0, DMATCR0, CHCR0 only dreq0-3 DDT module...
Page 433: Pin Configuration
14.1.3 Pin Configuration Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel Pin Name Abbreviation Function '5(43 DMA transfer Input DMA transfer request input from request external device to channel 0 '5(4 acceptance DRAK0 Output Acceptance of request for DMA confirmation transfer from channel 0 to external device...
Page 434: Register Configuration
Table 14.2 DMAC Pins in DDT Mode Pin Name Abbreviation Function '%5(4 Data bus request Input Data bus release request from external ('5(43) device for DTR format input %$9/ Data bus available Output Data bus release notification (DRAK0) Data bus can be used 2 cycles after %$9/ is asserted If asserted 2 cycles after %$9/ Transfer request signal...
Page 435 Table 14.3 DMAC Registers Chan- Abbre- Read/ Area 7 Access Name viation Write Initial Value P4 Address Address Size DMA source Undefined H'FFA00010 H'1FA00010 32 SAR1 address register 1 DMA destination Undefined H'FFA00014 H'1FA00014 32 DAR1 address register 1 DMA transfer DMATCR1 R/W Undefined H'FFA00018 H'1FA00018 32...
Page 436: Register Descriptions
14.2 Register Descriptions 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...
Page 437: Dma Destination Address Registers 0-3 (Dar0-Dar3)
14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...
Page 438: Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3)
14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: Initial value: R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — —...
Page 439: Dma Channel Control Registers 0-3 (Chcr0-Chcr3)
14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: SSA2 SSA1 SSA0 DSA2 DSA1 DSA0 Initial value: R/W: Bit: — — — — Initial value: — — — — R/W: (R/W) (R/W) Bit: Initial value: R/W: Bit: — Initial value: R/W: R/(W) Note: The TE bit can only be written with 0 after being read as 1, to clear the flag.
Page 440 Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. Bit 31: SSA2 Bit 30: SSA1 Bit 29: SSA0 Description...
Page 441 Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0 Description...
Page 442 '5(4 '5(4 '5(4 Select (DS): Specifies either low level detection or falling edge detection as the Bit 19—'5(4 sampling method for the '5(4 pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR3.
Page 443 Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode.
Page 444 Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: Bit 8: Description External request, dual address mode* (external address space → external address space) (Initial value) Setting prohibited External request, single address mode External address space →...
Page 445 Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer. Bit 7: TM Description Cycle steal mode (Initial value) Burst mode Setting possible with DTR format [57:55] (MD bits) Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. Bit 6: TS2 Bit 5: TS1 Bit 4: TS0...
Page 446 Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1.
Page 447: Dma Operation Register (Dmaor)
14.2.5 DMA Operation Register (DMAOR) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — Initial value: R/W: Bit: — —...
Page 448 Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0. Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for channel execution when transfer requests are made for a number of channels simultaneously. Bit 9: PR1 Bit 8: PR0 Description...
Page 449 Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing 0 after reading 1.
Page 450: Operation
14.3 Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.
Page 451 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Illegal address check (reflected in AE bit) NMIF, AE, TE = 0? Transfer request issued? Bus mode, transfer request mode, detection method Transfer (1 transfer unit) DMATCR - 1 → DMATCR Update SAR, DAR NMIF or DMATCR = 0?
Page 452: Dma Transfer Requests
14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.
Page 453 • External Request Acceptance Conditions 1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF, DMAOR.AE, and CHCR.TE are all 0, if an external request ('5(4: edge-detected) is input it will be held inside the DMAC until DMA transfer is either executed or canceled. Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated.
Page 454 Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer DMAC Transfer Transfer Transfer RS3 RS2 RS1 RS0 Request Source Request Signal Source Destination Bus Mode SCI transmitter SCTDR1 (SCI External* SCTDR1 Cycle steal transmit-data- mode empty transfer request) SCI receiver SCRDR1 (SCI...
Page 455: Channel Priorities
14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the relative channel priorities remain fixed.
Page 456 Transfer on channel 0 Channel 0 is given the lowest CH0 > CH1 > CH2 > CH3 Initial priority order priority. Priority order after transfer CH1 > CH2 > CH3 > CH0 Transfer on channel 1 When channel 1 is given the Initial priority order CH0 >...
Page 457 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby).
Page 458: Types Of Dma Transfer
14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output.
Page 459 Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer.
Page 460 CKIO Address output to external memory A28–A0 space Data output from external device D63–D0 with DACK DACK DACK signal to external device with DACK WE signal to external memory space (a) From external device with DACK to external memory space CKIO Address output to external memory A28–A0...
Page 461 memory in the write cycle. Figure 14.8 shows the timing for this operation. The DACK output timing is the same as that of &6Q in a read or write cycle specified by the CHCRn.AM bit. Memory DMAC Transfer source module Transfer destination Data buffer module...
Page 462 CKIO Transfer source Transfer destination A26–A0 address address D63–D0 DACK Data read cycle Data write cycle (1st cycle) (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0–...
Page 463 Bus returned to CPU Bus cycle DMAC DMAC DMAC DMAC Read, write Read, write Figure 14.9 Example of DMA Transfer in Cycle Steal Mode Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied.
Page 464 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the bus mode. Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Request Transfer Size...
Page 465 (a) DMAC Normal Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by the SH7750 Series in DMAC normal mode. Table 14.8 External Request Transfer Sources and Destinations in Normal Mode...
Page 466 Table 14.9 External Request Transfer Sources and Destinations in DDT Mode Usable Transfer Direction (Settable Memory Interface) Address DMAC Transfer Source Transfer Destination Mode Channels Synchronous DRAM External device with DACK Single 0, 1, 2, 3 (64-bit width) External device with DACK Synchronous DRAM Single 0, 1, 2, 3...
Page 467: Number Of Bus Cycle States And '5
DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 DMAC channel 1 DMAC channel 0 and DMAC channel 1 burst mode channel 1 round robin burst mode mode Priority system: Round robin mode Channel 0: Cycle steal mode Channel 1: Burst mode (edge-sensing)
Page 468 In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If '5(4 is not detected at this time, sampling is executed in every subsequent cycle.
Page 469 For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. '5(4 is not sampled during this time, and therefore DRAK is output in the first cycle only.
Page 470 Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → → → → External Bus/'5(4 '5(4 (Level Detection), DACK (Read Cycle) '5(4 '5(4 Rev. 4.0, 04/00, page 459 of 850...
Page 471 Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → → → → External Bus/'5(4 '5(4 (Edge Detection), DACK (Read Cycle) '5(4 '5(4 Rev. 4.0, 04/00, page 460 of 850...
Page 472 Figure 14.14 Dual Address Mode/Burst Mode External Bus → → → → External Bus/'5(4 '5(4 (Level Detection), DACK (Read Cycle) '5(4 '5(4 Rev. 4.0, 04/00, page 461 of 850...
Page 473 Figure 14.15 Dual Address Mode/Burst Mode External Bus → → → → External Bus/'5(4 '5(4 '5(4 (Edge Detection), DACK (Read Cycle) '5(4 Rev. 4.0, 04/00, page 462 of 850...
Page 474 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → → → → External Bus Rev. 4.0, 04/00, page 463 of 850...
Page 475 Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → → → → On-Chip SCI (Level Detection) Rev. 4.0, 04/00, page 464 of 850...
Page 476 Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → → → → External Bus/'5(4 '5(4 (Level Detection) '5(4 '5(4 Rev. 4.0, 04/00, page 465 of 850...
Page 477 Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → → → → External Bus/'5(4 '5(4 '5(4 (Edge Detection) '5(4 Rev. 4.0, 04/00, page 466 of 850...
Page 478 Figure 14.20 Single Address Mode/Burst Mode External Bus → → → → External Bus/'5(4 '5(4 (Level Detection) '5(4 '5(4 Rev. 4.0, 04/00, page 467 of 850...
Page 479 Figure 14.21 Single Address Mode/Burst Mode External Bus → → → → External Bus/'5(4 '5(4 (Edge Detection) '5(4 '5(4 Rev. 4.0, 04/00, page 468 of 850...
Page 480 Figure 14.22 Single Address Mode/Burst Mode External Bus → → → → External Bus/'5(4 '5(4 (Level Detection)/32-Byte Block Transfer '5(4 '5(4 (Bus Width: 64 Bits, SDRAM: Row Hit Write) Rev. 4.0, 04/00, page 469 of 850...
Page 481: Ending Dma Transfer
14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer.
Page 482 Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: • The value in the DMA transfer count register (DMATCR) reaches 0. • The DE bit in the DMA channel control register (CHCR) is cleared to 0. 1.
Page 483 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the CPU.
Page 484: Examples Of Use
14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here. Table 14.10 shows the transfer conditions and the corresponding register settings. Table 14.10 Conditions for Transfer between External Memory and an External Device with DACK, and Corresponding Register Settings Transfer Conditions...
Page 485: On-Demand Data Transfer Mode
14.5 On-Demand Data Transfer Mode 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and DDT module, and simultaneously issue a transfer request, using the '%5(4, %$9/, 75, 7'$&., and ID [1:0] signals between an external device and the DMAC.
Page 486 1. Normal data transfer mode (channel 0) %$9/ (the data bus available signal) is asserted in response to '%5(4 (the data bus request signal) from an external device. Two CKIO-synchronous cycles after %$9/ is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with 75 (the transfer request signal).
Page 487: Pins In Ddt Mode
14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. /DREQ0 /DRACK0 /DREQ1 /DACK0 SH7750 ID1, ID0/DRAK1, DACK1 External device D63–D0 A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode •...
Page 488 7'$&.: Reply strobe signal for external device from DMAC 7'$&. In the case of a read cycle, the SH7750 Series asserts 7'$&. in the same cycle in which valid read data is carried. In the case of a write cycle, the SH7750 Series asserts 7'$&. two cycles before the valid write data output cycle.
Page 489 • 011: Quadword size (64-bit) specification • 100: 32-byte block transfer specification • 101: Setting prohibited • 110: Request queue clear specification • 111: Transfer end specification Bit 60: Read/Write (R/W) • 0: Memory read specification • 1: Memory write specification Bits 59 and 58: Channel Number (ID1, ID0) •...
Page 490: Transfer Request Acceptance On Each Channel
= 111) when the required amount of data has been transferred. This will terminate DMA transfer on channel 0. In this case, the TE bit in DMA channel control register 0 is not set, but transfer cannot be restarted. 6. When port functions are used (BCR2.PORTEN = 1) and DDT mode is selected, input the DTR format for D[63:52] and D[31:0].
Page 491 Figure 14.26 Single Address Mode: Synchronous DRAM -> External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD = 1, CAS latency = 3, TPC = 3) Rev. 4.0, 04/00, page 480 of 850...
Page 492 Figure 14.27 Single Address Mode: External Device -> Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD = 1, TRWL = 2, TPC = 1) Rev. 4.0, 04/00, page 481 of 850...
Page 493 DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.28 Single Address Mode/Burst Mode/External Bus → → → → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.29 Single Address Mode/Burst Mode/External Device →...
Page 494 DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Bus → → → → External Device 64-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 4.0, 04/00, page 483 of 850...
Page 495 DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.31 Single Address Mode/Burst Mode/External Device → → → → External Bus 64-Bit Transfer/Channel 0 On-Demand Data Transfer Rev. 4.0, 04/00, page 484 of 850...
Page 496 DBREQ BAVL A25–A0 D63–D0 MD = 10 or 11 MD = 00 TDACK ID1, ID0 Next transfer request Start of data transfer Figure 14.32 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Rev. 4.0, 04/00, page 485 of 850...
Page 497 DBREQ BAVL A25–A0 D63–D0 MD = 10 or 11 TDACK ID1, ID0 Start of data transfer Next transfer request Figure 14.33 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Rev. 4.0, 04/00, page 486 of 850...
Page 498 DBREQ BAVL A25–A0 D2 D3 D63–D0 RAS, CAS, Figure 14.34 Read from Synchronous DRAM Precharge Bank DBREQ Transfer requests can be accepted BAVL A25–A0 D63–D0 RAS, CAS, Figure 14.35 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Rev. 4.0, 04/00, page 487 of 850...
Page 499 DBREQ BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.36 Read from Synchronous DRAM (Row Hit) DBREQ BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.37 Write to Synchronous DRAM Precharge Bank Rev. 4.0, 04/00, page 488 of 850...
Page 500 DBREQ Transfer requests can be accepted BAVL A25–A0 D63–D0 RAS, CAS, Figure 14.38 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) DBREQ BAVL A25–A0 D63–D0 RAS, CAS, Figure 14.39 Write to Synchronous DRAM (Row Hit) Rev. 4.0, 04/00, page 489 of 850...
Page 501 A25–A0 D63–D0 RAS, CAS, WE ID1, ID0 Figure 14.40 Single Address Mode/Burst Mode/External Bus → → → → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev. 4.0, 04/00, page 490 of 850...
Page 502 DMA Operation Register (DMAOR) PR[1:0] NMIF (SH7750S) DDT: 0: Normal DMA mode 1: On-demand data transfer mode Figure 14.41 DDT Mode Setting No DMA request sampling A25–A0 D63–D0 D1 D2 D3 D1 D2 MD = 01 ID1, ID0 Start of data transfer Figure 14.42 Single Address Mode/Burst Mode/Edge Detection/ External Device →...
Page 503 Wait for next DMA request A25–A0 D1 D2 D3 D0 D1 D2 D3 D63–D0 MD = 10 ID1, ID0 Start of data transfer Figure 14.43 Single Address Mode/Burst Mode/Level Detection/ External Bus → → → → External Device Data Transfer A25–A0 D63–D0 Idle cycle...
Page 504 A25–A0 D63–D0 MD = 01 DQMn Idle cycle Idle cycle Idle cycle ID1, ID0 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → → → → External Bus Data Transfer Rev. 4.0, 04/00, page 493 of 850...
Page 505 A25–A0 D63–D0 ID = 1, 2, or 3 RAS, CAS, WE ID1, ID0 01 or 10 or 11 Figure 14.46 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus Rev. 4.0, 04/00, page 494 of 850...
Page 506 DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 No DTR cycle, so requests can be made at any time Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → → → → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus Rev.
Page 507 Four requests can be queued Handshaking is necessary to send additional requests DBREQ BAVL No more requests A25–A0 D63–D0 D1 D2 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.48 Single Address Mode/Burst Mode/External Bus → → → → External Device Data Transfer/Direct Data Transfer Request to Channel 2 Rev.
Page 508 Four requests can be queued Handshaking is necessary to send additional requests DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.49 Single Address Mode/Burst Mode/External Device → → → → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 Rev.
Page 509 Handshaking is necessary Four requests can be queued to send additional requests DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Bus → → → → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Rev.
Page 510: Notes On Use Of Ddt Module
Four requests can be queued Handshaking is necessary to send additional requests DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.51 Single Address Mode/Burst Mode/External Device → → → → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 14.5.4 Notes on Use of DDT Module...
Page 511 c. In the SH7750S, initial settings can be made in the DMAC channel 0 control register from the CPU (possible settings are CHCR0.RS = 0000, 0010, or 0011). If settings of DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101 or 110 are subsequently input, a transfer request to channel 0 will be asserted.
Page 512 8. Data transfer end request a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0, transfer cannot be ended midway.
Page 513: Usage Notes
14.6 Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3, first clear the DE bit for the relevant channel to 0. 2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not operating.
Page 514: Section 15 Serial Communication Interface (Sci)
Section 15 Serial Communication Interface (SCI) 15.1 Overview The SH7750 is equipped with a single-channel serial communication interface (SCI) and a single- channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Page 515  Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors •...
Page 516: Block Diagram
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Internal Module data bus data bus SCSSR1 SCBRR1 SCRDR1 SCTDR1 SCSCR1 Pφ SCSMR1 SCRSR1 SCTSR1 Baud rate Pφ/4 SCSPTR1 generator Transmission/ Pφ/16 reception control Pφ/64 Clock Parity generation Parity check External clock SCRSR1: Receive shift register...
Page 517: Pin Configuration
15.1.3 Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK Clock input/output Receive data pin Input Receive data input Transmit data pin MD7/TxD Output Transmit data output Note: The serial clock pin and transmit data pin function as mode input pins MD0 and MD7 after a power-on reset.
Page 518: Register Descriptions
15.2 Register Descriptions 15.2.1 Receive Shift Register (SCRSR1) Bit: R/W: — — — — — — — — SCRSR1 is the register used to receive serial data. The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 519: Transmit Shift Register (Sctsr1)
15.2.3 Transmit Shift Register (SCTSR1) Bit: R/W: — — — — — — — — SCTSR1 is the register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCTDR1 to SCTSR1, and transmission started, automatically.
Page 520: Serial Mode Register (Scsmr1)
15.2.5 Serial Mode Register (SCSMR1) Bit: STOP CKS1 CKS0 Initial value: R/W: SCSMR1 is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SCSMR1 can be read or written to by the CPU at all times. SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state.
Page 521 Bit 4—Parity Mode (O/( ( ( ( ): Selects either even or odd parity for use in parity addition and checking. The O/( bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode.
Page 522: Serial Control Register (Scscr1)
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, the PE bit and O/( bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor Communication Function.
Page 523 Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and the TDRE flag in SCSSR1 is set to 1. Bit 7: TIE Description Transmit-data-empty interrupt (TXI) request disabled* (Initial value) Transmit-data-empty interrupt (TXI) request enabled Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0,...
Page 524 Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4: RE Description Reception disabled* (Initial value) Reception enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
Page 525 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial clock input pin.
Page 526: Serial Status Register (Scssr1)
15.2.7 Serial Status Register (SCSSR1) Bit: TDRE RDRF ORER TEND MPBT Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
Page 527 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data has been stored in SCRDR1. Bit 6: RDRF Description There is no valid receive data in SCRDR1 (Initial value) [Clearing conditions] • Power-on reset, manual reset, standby mode, or module standby •...
Page 528 Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4: FER Description Reception in progress, or reception has ended normally* (Initial value) [Clearing conditions] • Power-on reset, manual reset, standby mode, or module standby •...
Page 529 Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2: TEND Description Transmission is in progress [Clearing conditions]...
Page 530: Serial Port Register (Scsptr1)
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used, and when the operation is not transmission.
Page 531 Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0. Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0.
Page 532 Reset SPB1IO Internal data bus SPTRW Reset MD0/SCK SPB1DT SPTRW Clock output enable signal Mode setting Serial clock output signal register Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1.
Page 533 Reset SPB0IO Internal data bus SPTRW Reset MD7/TxD SPB0DT Transmit enable signal SPTRW Mode setting register Serial transmit data SPTRW: Write to SPTR Figure 15.3 MD7/TxD Pin Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 15.4 RxD Pin Rev.
Page 534: Bit Rate Register (Scbrr1)
15.2.9 Bit Rate Register (SCBRR1) Bit: Initial value: R/W: SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times. SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the module standby state.
Page 535 The bit rate error in asynchronous mode is found from the following equation: P × 10 φ × 100 Error (%) = – 1 (N + 1) × B × 64 × 2 2n–1 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode.
Page 536 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode Pφ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 0.16 0.21 0.00 0.16 1200...
Page 537 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) Pφ φ φ φ (MHz) 6.144 7.37288 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16...
Page 538 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont) Pφ φ φ φ (MHz) 14.7456 19.6608 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16...
Page 539 Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode Pφ φ φ φ (MHz) 28.7 Bit Rate (bits/s) — — — — — — — — — — — — — — 2.5k 100k 250k — — 500k —...
Page 540 Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ...
Page 541 Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 2.0000...
Page 542: Operation
15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8.
Page 543 Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings SCI Transfer Format Multi- Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: Data processor Parity Stop Bit C/$ $ $ $ STOP Mode Length Length Asynchronous 8-bit data 1 bit mode 2 bits...
Page 544: Operation In Asynchronous Mode
15.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by- character basis.
Page 545 Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings Serial Transfer Format and Frame Length CHR PE MP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data...
Page 546 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9.
Page 547 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits When clock output is selected in in SCSCR1 to 0 asynchronous mode, it is output immediately after SCSCR1 settings are made.
Page 548 1. SCI status check and transmit data Start of transmission write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear Read TDRE flag in SCSSR1 the TDRE flag to 0. 2.
Page 549 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2.
Page 550 Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDRE TEND TXI interrupt TXI interrupt request request TEI interrupt Data written to SCTDR1 request and TDRE flag cleared to 0 by TXI interrupt handler One frame Figure 15.9 Example of Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial...
Page 551 1. Receive error handling and Start of reception break detection: If a receive error occurs, read the ORER, PER, and FER flags in Read ORER, PER, and FER flags SCSSR1 to identify the error. in SCSSR1 After performing the appropriate error handling, ensure that the ORER, PER, PER or FER and FER flags are all cleared to...
Page 552 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR1 to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 Figure 15.10 Sample Serial Reception Flowchart (2) Rev.
Page 553 In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3.
Page 554: Multiprocessor Communication Function
Start Data Parity Stop Start Data Parity Stop Serial data RDRF RXI interrupt request SCRDR1 data read and ERI interrupt request RDRF flag cleared to 0 generated by framing One frame by RXI interrupt handler error Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 15.3.3 Multiprocessor Communication Function...
Page 555 Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle: Data transmission cycle: Receiving station Data transmission to...
Page 556 Start of transmission 1. SCI status check and ID data write: Read SCSSR1 and check that the Read TEND flag in SCSSR1 TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1. Finally, clear the TDRE flag to 0.
Page 557 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2.
Page 558 Multi- Multi- Multi- Start Data Stop Start Data Stop Start Data Stop proces- proces- proces- sor bit sor bit sor bit Serial Idle state D0 D1 D0 D1 D0 D1 data (mark state) TDRE TEND Data written to SCTDR1 TXI interrupt One frame and TDRE flag cleared request...
Page 559 1. ID reception cycle: Set the MPIE Start of reception bit in SCSCR1 to 1. 2. SCI status check, ID reception Set MPIE bit in SCSCR1 to 1 and comparison: Read SCSSR1 and check that the RDRF flag is Read ORER and FER flags set to 1, then read the receive in SCSSR1 data in SCRDR1 and compare it...
Page 560 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 4.0, 04/00, page 549 of 850...
Page 561 Figure 15.16 shows an example of SCI operation for multiprocessor format reception. Data Start Stop Start Stop Data (ID1) (Data1) Serial Idle state data (mark state) MPIE RDRF SCRDR1 value RXI interrupt request SCRDR1 data read As data is not this RXI interrupt request (multiprocessor and RDRF flag...
Page 562: Operation In Synchronous Mode
In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3.
Page 563 In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In serial communication, one character consists of data output starting with the LSB and ending with the MSB.
Page 564 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Clear TE and RE bits 2. Set the data transfer format in in SCSCR1 to 0 SCSMR1. 3.
Page 565 Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit Start of transmission data write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to Read TDRE flag in SCSSR1...
Page 566 In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2.
Page 567 Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0.
Page 568 Error handling ORER = 1? Overrun error handling Clear ORER flag in SCSSR1 to 0 Figure 15.21 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2.
Page 569 Transfer direction Serial clock Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data RDRF ORER Data read from RXI interrupt ERI interrupt RXI interrupt SCRDR1 and RDRF request request due to request flag cleared to 0 in RXI overrun error interrupt handler One frame...
Page 570 1. SCI status check and transmit data Start of transmission/reception write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear Read TDRE flag in SCSSR1 the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt.
Page 571: Sci Interrupt Sources And Dmac
15.4 SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1.
Page 572: Usage Notes
15.5 Usage Notes The following points should be noted when using the SCI. SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data from SCTDR1 to SCTSR1, the TDRE flag is set to 1.
Page 573 Sending a Break Signal: The input/output condition and level of the TxD pin are determined by bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send a break signal. After the serial transmitter is initialized, the TxD pin function is not selected and the value of the SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e.
Page 574 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks...
Page 575 When Using the DMAC: When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles after SCTDR1 is updated.
Page 576: Section 16 Serial Communication Interface With Fifo (Scif)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview The SH7750 is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication. Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication.
Page 577 • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. • The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. •...
Page 578: Block Diagram
16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Internal Module data bus data bus SCBRR2 SCFRDR2 SCSMR2 SCFTDR2 (16-stage) (16-stage) SCLSR2 SCFDR2 Pφ SCFCR2 RxD2 SCRSR2 SCTSR2 SCFSR2 Baud rate Pφ/4 generator SCSCR2 SCSPTR2 Pφ/16 Transmission/ Pφ/64 reception control...
Page 579: Pin Configuration
16.1.3 Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Abbreviation Function Serial clock pin MRESET/SCK2 Input Clock input Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output Transmit data output &765 Modem control pin Transmission enabled...
Page 580: Register Configuration
16.1.4 Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Abbrevia- Initial Area 7 Access Name tion Value Address...
Page 581: Receive Fifo Data Register (Scfrdr2)
16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: R/W: SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for reception, and consecutive receive operations can be performed until the receive FIFO register is full (16 data bytes).
Page 582: Transmit Fifo Data Register (Scftdr2)
16.2.4 Transmit FIFO Data Register (SCFTDR2) Bit: R/W: SCFTDR2 is a 16-stage FIFO register that stores data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission. SCFTDR2 is a write-only register, and cannot be read by the CPU.
Page 583 Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR Description 8-bit data (Initial value) 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception.
Page 584: Serial Control Register (Scscr2)
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character.
Page 585 Bits 15 to 8, 2, and 0—Reserved: These bits are always read as 0, and should only be written with 0. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1.
Page 586 Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCIF. Bit 4: RE Description Reception disabled* (Initial value) Reception enabled* Notes: 1. Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states.
Page 587: Serial Status Register (Scfsr2)
16.2.7 Serial Status Register (SCFSR2) Bit: PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: R/W: Bit: TEND TDFE Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register.
Page 588 Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception. Bit 7: ER Description No framing error or parity error occurred during reception (Initial value) [Clearing conditions] • Power-on reset or manual reset • When 0 is written to ER after reading ER = 1 A framing error or parity error occurred during reception [Setting conditions] •...
Page 589 Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description Transmission is in progress [Clearing conditions] • When transmit data is written to SCFTDR2, and 0 is written to TEND after reading TEND = 1 •...
Page 590 Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2.
Page 591 Bit 3—Framing Error (FER): Indicates a framing error in the data read from SCFRDR2. Bit 3: FER Description There is no framing error in the receive data read from SCFRDR2 (Initial value) [Clearing conditions] • Power-on reset or manual reset •...
Page 592 Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2).
Page 593: Bit Rate Register (Scbrr2)
Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received. Bit 0: DR Description Reception is in progress or has ended normally and there is no receive data...
Page 594: Fifo Control Register (Scfcr2)
The SCBRR2 setting is found from the following equation. Asynchronous mode: φ P × 10 – 1 64 × 2 × B 2n–1 Where B: Bit rate (bits/s) N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255) Pφ: Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.)
Page 595 SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in standby mode or in the module standby state.
Page 596 Bits 5 and 4—Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the following table.
Page 597: Fifo Data Count Register (Scfdr2)
Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive input pin (RxD2), and the 5765 pin and &765 pin, enabling loopback testing. Bit 0: LOOP Description Loopback test disabled (Initial value) Loopback test enabled 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2.
Page 598: Serial Port Register (Scsptr2)
16.2.11 Serial Port Register (SCSPTR2) Bit: — — — — — — — — Initial value: R/W: Bit: RTSIO RTSDT CTSIO CTSDT — — SPB2IO SPB2DT Initial value: — — — R/W: SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins.
Page 599 Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port 5765 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details). In output mode, the RTSDT bit value is output to the 5765 pin. The 5765 pin value is read from the RTSDT bit regardless of the value of the RTSIO bit.
Page 600 Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin.
Page 601 Reset CTSIO Internal data bus SPTRW Reset CTS2 CTSDT SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 &765 &765 Pin &765...
Page 602 Reset SPB2IO Internal data bus SPTRW Reset MD1/TxD2 SPB2DT SCIF Transmit enable SPTRW signal Mode setting register Serial transmit data SPTRW: Write to SPTR Figure 16.4 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register Internal data bus SPTRR SPTRR: Read SPTR Figure 16.5 MD2/RxD2 Pin Rev.
Page 603 Reset SCKIO Internal data bus SPTRW Reset MRESET/ SCK2 SCKDT SCIF SPTRW Clock output enable signal Serial clock output signal Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR2.
Page 604: Line Status Register (Sclsr2)
16.2.12 Line Status Register (SCLSR2) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — ORER Initial value: R/W: (R/W)* Note: * Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Page 605: Operation
16.3 Operation 16.3.1 Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed.
Page 606: Serial Operation
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection SCSCR2 Setting SCIF Transmit/Receive Clock Bit 1: CKE1 Mode Clock Source SCK2 Pin Function Asynchronous mode Internal SCIF does not use SCK2 pin External Inputs clock with frequency of 16 times the bit rate 16.3.2 Serial Operation Data Transfer Format...
Page 607 Table 16.5 Serial Transfer Formats SCSMR2 Settings Serial Transfer Format and Frame Length CHR PE STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP Start bit...
Page 608 Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 609 1. Set the clock selection in SCSCR2. Initialization Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits 2. Set the data transfer format in in SCSCR2 to 0 SCSMR2. 3.
Page 610 Serial Data Transmission: Figure 16.8 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data Start of transmission write: Read SCFSR2 and check that the Read TDFE flag in SCFSR2 TDFE flag is set to 1, then write transmit data to SCFTDR2, read 1...
Page 611 In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2.
Page 612 Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame Figure 16.9 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
Page 613 Serial Data Reception: Figure 16.11 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag Read ER, DR, BRK flags in in SCLSR2, to identify any...
Page 614 1. Whether a framing error or parity error Error handling has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in ORER = 1? SCFSR2. 2. When a break signal is received, receive data is not transferred to Overrun error handling SCFRDR2 while the BRK flag is set.
Page 615 In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3.
Page 616 Start Data Parity Stop Start Data Parity Stop Serial data RXI interrupt request Data read and RDF flag ERI interrupt request read as 1 then cleared to generated by receive One frame 0 by RXI interrupt handler error Figure 16.12 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5.
Page 617: Scif Interrupt Sources And The Dmac
16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receive- error interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 16.6 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR2.
Page 618: Usage Notes
See section 5, Exceptions, for priorities and the relationship with non-SCIF interrupts. 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag: The TDFE flag in the serial status register (SCFSR2) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR2) has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2).
Page 619 After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled). The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) beforehand.
Page 620 From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2). When D = 0.5 and F = 0: M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ..........(2) This is a theoretical value.
Page 621 Flow chart: Framing error occurrence When flaming error (SCFSR. ER=1) is occurred, bit7 to bit0 should be read out from SCFDR2. If bit7 to bit0 Bits 7 to 0 in SCFDR2 = H'10? equals H'10, contents of the RxFIFO should be read. When the data received last is not accompanied with flaming error (SCFSR2.
Page 622: Section 17 Smart Card Interface
Section 17 Smart Card Interface 17.1 Overview An IC card (smart card) interface conforming to ISO/IEC 7816-3 (Identification Card) is supported as a serial communication interface (SCI) extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting.
Page 623: Block Diagram
17.1.2 Block Diagram Figure 17.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCSCMR1 SCBRR1 SCRDR1 SCTDR1 SCSSR1 Pφ SCSCR1 SCRSR1 SCTSR1 Baud rate SCSMR1 Pφ/4 generator SCSPTR1 Pφ/16 Transmission/ reception control Pφ/64 Clock Parity generation Parity check...
Page 624: Pin Configuration
17.1.3 Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK Clock input/output Receive data pin Input Receive data input Transmit data pin MD7/TxD Output Transmit data output 17.1.4 Register Configuration...
Page 625: Register Descriptions
17.2 Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state.
Page 626: Serial Mode Register (Scsmr1)
Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF Description Smart card interface function is disabled (Initial value) Smart card interface function is enabled 17.2.2 Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode. Bit: GM(C/$) STOP...
Page 627: Serial Control Register (Scscr1)
17.2.3 Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode. Bit: — — CKE1 CKE0 Initial value: R/W: Bits 7 to 4: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface, for details.
Page 628: Serial Status Register (Scssr1)
17.2.4 Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: TDRE RDRF ORER FER/ TEND — — Initial value: R/W: R/(W)* R/(W)*...
Page 629: Operation
Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND Description Transmission in progress [Clearing condition] • When 0 is written to TDRE after reading TDRE = 1 Transmission has been ended (Initial value) [Setting conditions] •...
Page 630: Pin Connections
17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the V CC power supply side with a resistor.
Page 631: Data Format
17.3.3 Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data.
Page 632: Register Settings
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor.
Page 633 I/O data Ds Da Db Dc Dd De Dg Dh Dp Guard time 12.5 etu GM = 0 (TEND interrupt) 11.0 etu GM = 1 Figure 17.4 TEND Generation Timing Bit Rate Register (SCBRR1) Setting: SCBRR1 is used to set the bit rate. See section 17.3.5, Clock, for the method of calculating the value to be set.
Page 634: Clock
State (a) Direct convention (SDIR = SINV = O/ = 0) State (b) Inverse convention (SDIR = SINV = O/ = 1) Figure 17.5 Sample Start Character Waveforms 17.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface.
Page 635 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) Pφ φ φ φ (MHz) 7.1424 10.00 10.7136 14.2848 25.0 33.0 50.0 9600.0 13440.9 14400.0 19200.0 33602.2 44354.8 67204.3 4800.0 6720.4 7200.0 9600.0 16801.1 22177.4 33602.2 3200.0...
Page 636 The bit rate error is given by the following equation: P φ × 10 – 1 × 100 Error (%) = 1488 × 2 × B × (N + 1) 2n–1 Table 17.8 shows the relationship between the smart card interface transmit/receive clock register settings and the output state.
Page 637: Data Transfer Operations
17.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. Figure 17.7 shows a sample initialization processing flowchart. 1.
Page 638 Initialization Clear TE and RE bits in SCSCR1 to 0 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 In SCSMR1, set parity in O/ bit, clock in CKS1 and CKS0 bits, and set GM Set SMIF, SDIR, and SINV bits in SCSCMR1 Set value in SCBRR1 In SCSCR1, set clock in CKE1...
Page 639 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2.
Page 640 Start Initialization Start of transmission FER/ERS = 0? Error handling TEND = 1? Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit in SCSCR1 to 0 End of transmission Figure 17.8 Sample Transmission Processing Flowchart Rev.
Page 641 Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform the appropriate receive error handling, then clear both the ORER and the PER flag to 0.
Page 642 Start Initialization Start of reception ORER = 0 and PER = 0? Error handling RDRF = 1? Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 All data received? Clear RE bit in SCSCR1 to 0 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm...
Page 643 Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated. When the RDRF flag in SCSSR1 is set to 1, an RXI interrupt request is generated.
Page 644: Usage Notes
17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. (1) Receive Data Sampling Timing and Receive Margin In asynchronous mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate.
Page 645 From the above equation, if F = 0 and D = 0.5, the receive margin is 49.866%, as given by the following equation. When D = 0.5 and F = 0: M = (0.5 – 1/2 × 372) × 100% = 49.866% (2) Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below.
Page 646 Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving side after transmission of one frame is completed, the FER/ERS bit in SCSSR1 is set to 1. If the RIE bit in SCSCR1 is enabled at this time, an ERI interrupt request is generated.
Page 647 (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1. Set the SBP1IO and SBP1DT bits in SCSPTR1 to the values for the fixed output state in standby mode.
Page 648 (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential. 2. Fix at the output specified by the CKE1 bit in the serial control register (SCSCR1). 3.
Page 649: Section 18 I/O Ports
Section 18 I/O Ports 18.1 Overview The SH7750 has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: • 20-bit I/O port with input/output direction independently specifiable for each bit •...
Page 650: Block Diagrams
18.1.2 Block Diagrams Figure 18.1 shows a block diagram of the 16-bit general-purpose I/O port. PBnPUP Pull-up resistor PORTEN Internal bus Port 15 (input/ Dn output data output)/D47 Port 0 (input/ output)/D32 PDTRW DnDIR PBnIO Data input strobe Interrupt PTIRENn Dn input data controller PORTEN...
Page 651 Figure 18.2 shows a block diagram of the 4-bit general-purpose I/O port. PBnPUP Pull-up resistor PORTEN Internal bus Port 19 (input/ Dn output data output)/D51 Port 16 (input/ PDTRW output)/D48 DnDIR PBnIO Data input strobe Dn input data PORTEN 0: Port not available 1: Port available PBnPuP 0: Pull-up 1: Pull-up off...
Page 652 SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset SPB1IO Internal data bus SPTRW Reset MD0/SCK SPB1DT SPTRW Clock output enable signal Mode setting Serial clock output signal register Serial clock input signal Clock input enable signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR...
Page 653 Reset SPB0IO Internal data bus SPTRW Reset MD7/TxD SPB0DT Transmit enable signal SPTRW Mode setting register Serial transmit data SPTRW: Write to SPTR Figure 18.4 MD7/TxD Pin Serial receive data Internal data bus SPTRR SPTRR: Read SPTR Figure 18.5 RxD Pin Rev.
Page 654 SCIF I/O port block diagrams are shown in figures 18.6 to 18.9. Reset SPB2IO Internal data bus SPTRW Reset MD1/TxD2 SPB2DT SCIF Transmit enable SPTRW signal Mode setting register Serial transmit data SPTRW: Write to SPTR Figure 18.6 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive...
Page 655 Reset CTSIO Internal data bus SPTRW Reset CTS2 CTSDT SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function. Figure 18.8 &765 &765 Pin &765...
Page 656 Reset RTSIO Internal data bus SPTRW Reset MD8/RTS2 RTSDT SCIF Modem control SPTRW enable signal* Mode setting register RTS2 signal SPTRR SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function. 5765 5765 Pin 5765...
Page 657: Pin Configuration
18.1.3 Pin Configuration Table 18.1 shows the 20-bit general-purpose I/O port pin configuration. Table 18.1 20-Bit General-Purpose I/O Port Pins Pin Name Signal Function Port 19 pin PORT19 I/O port Port 18 pin PORT18 I/O port Port 17 pin PORT17 I/O port Port 16 pin PORT16...
Page 658 Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK Clock input/output Receive data pin Input Receive data input Transmit data pin MD7/TxD Output Transmit data output Note: Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on reset.
Page 659: Register Configuration
18.1.4 Register Configuration The 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Area 7 Access Name Abbreviation R/W Initial Value* P4 Address Address Size Port control register A PCTRA H'00000000...
Page 660: Register Descriptions
18.2 Register Descriptions 18.2.1 Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port should be set to output with PCTRA after writing a value to the PDTRA register.
Page 661: Port Data Register A (Pdtra)
Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16- bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO. Bit 2n + 1: PBnPUP Description Bit m (m = 0–15) of 16-bit port is pulled up...
Page 662: Port Control Register B (Pctrb)
18.2.3 Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 4-bit port (port 19 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 4-bit port should be set to output with PCTRB after writing a value to the PDTRB register.
Page 663: Port Data Register B (Pdtrb)
Bit 2n (n = 0–3)—Port I/O Control (PBnIO): Specifies whether each bit in the 4-bit port is an input or an output. Bit 2n: PBnIO Description Bit m (m = 16–19) of 4-bit port is an input (Initial value) Bit m (m = 16–19) of 4-bit port is an output 18.2.4 Port Data Register B (PDTRB) Port data register B (PDTRB) is a 16-bit readable/writable register used as a data latch for each bit...
Page 664: Serial Port Register (Scsptr1)
Bit: PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 PTIREN8 Initial value: R/W: Bit: PTIREN7 PTIREN6 PTIREN5 PTIREN4 PTIREN3 PTIREN2 PTIREN1 PTIREN0 Initial value: R/W: Bit n (n = 0–15)—Port Interrupt Enable (PTIRENn): Specifies whether interrupt input is performed for each bit. Bit n: PTIRENn Description Port m (m = 0–15) of 16-bit port is used as a normal I/O port (Initial value)
Page 665 Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0. Bit 3: SPB1IO Description SPB1DT bit value is not output to the SCK pin...
Page 666: Serial Port Register (Scsptr2)
18.2.7 Serial Port Register (SCSPTR2) Bit: — — — — — — — — Initial value: R/W: Bit: RTSIO RTSDT CTSIO CTSDT — — SPB2IO SPB2DT Initial value: — — — R/W: The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins.
Page 667 Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port 5765 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the 5765 pin is designated as an output, the value of the RTSDT bit is output to the 5765 pin.
Page 668 Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin.
Page 669: Section 19 Interrupt Controller (Intc)
Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority. 19.1.1 Features The INTC has the following features.
Page 670 SCIF: Serial communication interface with FIFO WDT: Watchdog timer REF: Memory refresh controller section of the bus state controller DMAC: Direct memory access controller H-UDI: Hitachi user debug interface GPIO: I/O port ICR: Interrupt control register IPRA–IPRD: Interrupt priority registers A–D* Status register Note: * IPRD is provided only in the SH7750S.
Page 671: Pin Configuration
19.1.3 Pin Configuration Table 19.1 shows the INTC pin configuration. Table 191 INTC Pins Pin Name Abbreviation Function Nonmaskable interrupt Input Input of nonmaskable interrupt request input pin signal ,5/6–,5/3 Interrupt input pins Input Input of interrupt request signals (maskable by I3–I0 in SR) 19.1.4 Register Configuration The INTC has the registers shown in table 19.2.
Page 672: Interrupt Sources
19.2 Interrupt Sources There are three types of interrupt sources: NMI, RL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 19.2.1 NMI Interrupt The NMI interrupt has the highest priority level of 16.
Page 673: Irl Interrupts
IRL interrupts are input by level at pins ,5/6–,5/3. The priority level is the level indicated by pins ,5/6–,5/3. An ,5/6–,5/3 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). SH7750 Series Priority Interrupt encoder requests Figure 19.2 Example of IRL Interrupt Connection...
Page 674 Table 19.3 ,5/6 ,5/6 ,5/6 ,5/6–,5/3 ,5/3 ,5/3 ,5/3 Pins and Interrupt Levels ,5/6 ,5/6 ,5/5 ,5/5 ,5/4 ,5/4 ,5/3 ,5/3 ,5/6 ,5/6 ,5/5 ,5/5 ,5/4 ,5/4 ,5/3 ,5/3 Interrupt Priority Level Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request...
Page 675: On-Chip Peripheral Module Interrupts
IRL3 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following nine modules: • Hitachi user debug interface (H-UDI) • Direct memory access controller (DMAC) • Timer unit (TMU) • Realtime clock (RTC) • Serial communication interface (SCI) •...
Page 676: Interrupt Exception Handling And Priority
If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0. In this case, interrupt handling is initiated due to the timing relationship between the flag update and interrupt request recognition within the chip.
Page 677 Table 19.5 Interrupt Exception Handling Sources and Priority Order INTEVT Interrupt Priority IPR (Bit Priority within Default Interrupt Source Code (Initial Value) Numbers) IPR Setting Unit Priority H'1C0 — — High ↑ ,5/6–,5/3 = 0 H'200 — —   ,5/6–,5/3 = 1 H'220 ...
Page 678 RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt H-UDI: Hitachi use debug interface GPIOI: I/O port interrupt DMTE0–DMTE3: DMAC transfer end interrupts DMAE: DMAC address error interrupt * Interrupt priority levels can only be changed in the SH7750S. In the SH7750, the initial values cannot be changed.
Page 679: Register Descriptions
19.3 Register Descriptions 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are initialized to H'0000 by a reset. They are not initialized in standby mode. IPRA to IPRC Bit: Initial value:...
Page 680: Interrupt Control Register (Icr)
Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers Bits Register 15–12 11–8 7–4 3–0 Interrupt priority register A TMU0 TMU1 TMU2 Interrupt priority register B REF* SCI1 Reserved* Interrupt priority register C GPIO DMAC SCIF H-UDI Interrupt priority register D* IRL0 IRL1 IRL2...
Page 681 Bit 15: NMIL Description NMI pin input level is low NMI pin input level is high Bit 14—NMI Interrupt Mask (MAI): Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the CPU’s SR.BL bit. Bit 14: MAI Description Interrupts enabled even while NMI pin is low...
Page 682: Intc Operation
Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written with 0. 19.4 INTC Operation 19.4.1 Interrupt Operation Sequence The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations.
Page 683 Program execution state Interrupt generated? (BL bit in SR = 0) or (sleep or standby mode)? NMIB in ICR = 1 and NMI? NMI? Level 15 interrupt? Level 14 interrupt? I3–I0* = level 14 or lower? Level 1 interrupt? I3–I0 = level 13 or Set interrupt source lower?
Page 684: Multiple Interrupts
19.4.2 Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2.
Page 685: Interrupt Response Time
19.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 19.7. Table 19.7 Interrupt Response Time Number of States Peripheral Item...
Page 686: Section 20 User Break Controller (Ubc)
Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective self- monitoring debugger, enabling programs to be debugged with the chip alone, without using an in- circuit emulator.
Page 687: Block Diagram
20.1.2 Block Diagram Figure 20.1 shows a block diagram of the UBC. Access Address Data control Channel A Access BBRA comparator BARA Address BASRA comparator BAMRA Channel B Access BBRB comparator BARB Address BASRB comparator BAMRB BDRB Data comparator BDMRB BBRA: Break bus cycle register A BARA:...
Page 688 Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Break address BARA Undefined H'FF200000 H'1F200000 register A Break address BAMRA Undefined H'FF200004 H'1F200004 mask register A Break bus BBRA H'0000 H'FF200008...
Page 689: Register Descriptions
2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the SH7750 Series executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted.
Page 690: Break Address Register A (Bara)
20.2.2 Break Address Register A (BARA) Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value: R/W: Bit: BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: R/W: Bit: BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 Initial value: R/W: Bit: BAA7...
Page 691: Break Asid Register A (Basra)
20.2.3 Break ASID Register A (BASRA) Bit: BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 Initial value: R/W: Note: *: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions. BASRA is not initialized by a power-on reset or manual reset.
Page 692: Break Bus Cycle Register A (Bbra)
Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address (BAA31–BAA0) set in BARA are to be masked. Bit 3: BAMA2 Bit 1: BAMA1 Bit 0: BAMA0 Description All BARA bits are included in break conditions Lower 10 bits of BARA are masked, and not included in break conditions...
Page 693 Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 Bit 4: IDA0 Description Condition comparison is not performed (Initial value)
Page 694: Break Address Register B (Barb)
20.2.6 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register.
Page 695: Break Data Mask Register B (Bdmrb)
Bits 31 to 0—Break Data B31 to B0 (BDB31–BDB0): These bits hold the data (bits 31–0) to be used in the channel B break conditions. 20.2.10 Break Data Mask Register B (BDMRB) Bit: BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 Initial value: R/W: Bit:...
Page 696: Break Bus Cycle Register B (Bbrb)
Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data (BDB31–BDB0) set in BDRB is to be masked. Bit 31–0: BDMBn Description Channel B break data bit BDBn is included in break conditions Channel B break data bit BDBn is masked, and not included in break conditions n = 31 to 0...
Page 697 Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0 (to confirm that the flag is set again after once being set, it should be cleared with a write.) Bit 15: CMFA Description Channel A break condition is not matched...
Page 698: Operation
Bit 6—PC Break Select B (PCBB): Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. This bit is not initialized by a power-on reset or manual reset. Bit 6: PCBB Description Channel B PC break is effected before instruction execution Channel B PC break is effected after instruction execution...
Page 699: Explanation Of Terms Relating To Instruction Intervals
The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. The SH7750 Series handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA, and OCBI instructions is treated as longword.
Page 700: User Break Operation Sequence
20.3.3 User Break Operation Sequence The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions, in the break control register (BRCR).
Page 701: Instruction Access Cycle Break
20.3.4 Instruction Access Cycle Break 1. When an instruction access/read/word setting is made in the break bus cycle register (BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in the break control register (BRCR).
Page 702: Operand Access Cycle Break
20.3.5 Operand Access Cycle Break 1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in the break bus cycle register (BBRA/BBRB). Data Size Address Bits Compared Quadword (100) Address bits A31–A3...
Page 703: Condition Match Flag Setting
20.3.6 Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed.
Page 704: Contiguous A And B Settings For Sequential Conditions
4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed.
Page 705: Usage Notes
3. Operand access match on channel A, instruction access match on channel B Instruction B is 0 to 3 instructions after Sequential operation is not guaranteed. instruction A Instruction B is 4 or more instructions Sequential operation is guaranteed. after instruction A 4.
Page 706: User Break Debug Support Function
e. In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction).
Page 707 Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Trap Exception/ interrupt/trap? Interrupt EXPEVT ← exception code INTEVT ← interrupt code TRA ← TRAPA (imm) SGR ← R15 Reset exception? (BRCR.UBDE == 1) &&...
Page 708: Examples Of Use
20.5 Examples of Use Instruction Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode ...
Page 709  Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle.
Page 710: User Break Controller Stop Function
20.6 User Break Controller Stop Function In the SH7750S, this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller.
Page 711: Examples Of Stopping And Restarting The User Break Controller
20.6.3 Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. #0, R0 mov.l #BBRA, R1 mov.w R0, @R1 mov.l #BBRB, R1 mov.w R0, @R1...
Page 712: Section 21 Hitachi User Debug Interface (H-Udi)
21.1.1 Features The Hitachi user debug interface (H-UDI) is a serial input/output interface conforming to JTAG, IEEE 1149.1, and IEEE Standard Test Access Port and Boundary-Scan Architecture. The SH7750’s H-UDI does not support boundary-scan, but is used for emulator connection. The functions of this interface should not be used when using an emulator.
Page 713 Interrupt/reset etc. Break /BRKACK control Decoder controller SDIR SDBPR SDDRH SDDRL Figure 21.1 Block Diagram of H-UDI Circuit Rev. 4.0, 04/00, page 704 of 850...
Page 714: Pin Configuration
7567 alone. The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or SH7750 Series CPG setting so that the TCK frequency is lower than that of the SH7750 Series’ on-chip peripheral module clock.
Page 715: Register Configuration
21.1.4 Register Configuration Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the control register space and can be referenced by the CPU. Table 21.2 H-UDI Registers CPU Side H-UDI Side Abbre- Area 7 Access Initial Access Initial...
Page 716: Register Descriptions
21.2 Register Descriptions 21.2.1 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the 7567 pin or in the TAP Test-Logic-Reset state.
Page 717: Data Register (Sddr)
21.2.2 Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by a 7567 or CPU reset. Bit: Initial value: R/W:...
Page 718: Operation
21.3 Operation 21.3.1 TAP Control Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. • The transition condition is the TMS value at the rising edge of TCK. • The TDI value is sampled at the rising edge of TCK, and shifted at the falling edge. •...
Page 719: H-Udi Reset
3 to 0 of control register IPRC. The H-UDI interrupt request signal is asserted for about eight SH7750 Series on-chip peripheral clock cycles after the command is set. The number of assertion cycles is determined by the ratio of TCK to the on-chip peripheral clock frequency.
Page 720: Usage Notes
3. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used. 4. The SH7750 Series’ H-UDI pins must not be connected to a boundary-scan signal loop on the board. Rev. 4.0, 04/00, page 711 of 850...
Page 721: Section 22 Pin Description
Section 22 Pin Description 22.1 Pin Arrangement MD1/TXD2 MD0/SCK ...
Page 722 MD2/RXD2 MD1/TXD2 MD0/SCK QFP208 Top view VDD (internal, 1.8 V) VSS (internal, 0 V) VDDQ (IO, 3.3 V) VSSQ (IO, 0 V) Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal resonator, and RTC are used.
Page 723: Pin Functions
22.2 Pin Functions 22.2.1 Pin Functions (256-Pin BGA) Table 22.1 Pin Functions Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 5'< 5'< 5'< 5'< Bus ready 5(6(7 5(6(7 Reset &63 &63 &63 Chip select 0 &64 &64 &64 Chip select 1 &67...
Page 724 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data/port (Port) (Port)
Page 725 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset %$&./ %65(4 acknowledge/ bus request %5(4/ %6$&. request/bus acknowledge Data Data Clock output enable VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) :(8/&$68/ &$68 D47–D40...
Page 726 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Address Address Address CKIO Clock output CKIO VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) CKIO2...
Page 727 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 115 W16 RD/:5 Read/write RD/:5 RD/:5 RD/:5 :(5/&$65/ &$65 ,&,25' 116 Y17 D23–D16 DQM2 DQM2/ select signal ,&,25' :(6/&$66/ &$66 ,&,2:5 117 W17 D31–D24 DQM3 DQM3/ select signal...
Page 728 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 142 R20 Data 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSSQ Power IO GND (0 V) 145 P19 Data 146 P20 Data 147 N19 Data...
Page 729 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 174 E19 Data ACCSIZE2 175 F18 VDDQ Power IO VDD (3.3 V) 176 F17 VSSQ Power IO GND (0 V) 177 E17 VSSQ Power IO GND (0 V) 178 E18 RD/:55 = RD/:5...
Page 730 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 198 D15 VSSQ Power IO GND (0 V) 199 B15 MD7/TXD Mode/SCI data output 05(6(7 SCK2 200 A16 SCK2/ SCIF clock/ SCK2 SCK2 SCK2 SCK2 05(6(7 manual reset...
Page 731 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 225 D8 Address 226 A8 STATUS0 Status 227 B8 STATUS1 Status ,2,649 228 A7 MD6/ Mode/,2,649 ,2,649 (PCMCIA) 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSSQ Power IO GND (0 V)
Page 732 Table 22.1 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 248 A1 EXTAL External input clock/crystal resonator 249 C5 250 D16 251 H17 252 H18 253 N3 254 N4 255 U4 256 V18 Input Output I/O: Input/output...
Page 733: Pin Functions (208-Pin Qfp)
22.2.2 Pin Functions (208-Pin QFP) Table 22.2 Pin Functions Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset 5'< 5'< 5'< 5'< Bus ready 5(6(7 5(6(7 Reset &63 &63 &63 Chip select 0 &64 &64 &64 Chip select 1 &67 &67 &67...
Page 734 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data Data Data Data Data Data Power Internal VDD (1.8 V) Power Internal GND (0 V) Data...
Page 735 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset :(7/&$67/ &$67 D39–D32 select DQM4 DQM4 signal :(4/&$64/ &$64 D15–D8 select DQM1 DQM1 signal :(3/&$63/ &$63 D7–D0 select DQM0 DQM0 signal Address Address Address Power Internal VDD (1.8 V)
Page 736 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset VSSQ Power IO GND (0 V) &66 &66 &66 &66 Chip select 3 (&66) &65 &65 &65 &65 Chip select 2 (&65) Power Internal VDD (1.8 V) Power Internal GND...
Page 737 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset VSSQ Power IO GND (0 V) Data Data Power Internal VDD (1.8 V) Power Internal GND (0 V) Data Data Data Data Data Data VDDQ Power IO VDD (3.3 V)
Page 738 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Data/port (Port) (Port) (Port) (Port) (Port) Data ACCSIZE2 VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) MD0/SCK Mode/SCI clock MD1/TXD2 Mode SCIF data TXD2 TXD2...
Page 739 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Power Internal VDD (1.8 V) Power Internal GND (0 V) Address Address Address Address Address Address VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Address Address...
Page 740 Table 22.2 Pin Functions (cont) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Power Internal VDD (1.8 V) Power Internal GND (0 V) Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) 7567 Reset (H-UDI) VDD-PLL2 Power PLL2 VDD (3.3V) VSS-PLL2 Power PLL2 GND (0V)
Page 741: Section 23 Electrical Characteristics
Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 Absolute Maximum Ratings Item Symbol Value Unit I/O, PLL, RTC power supply voltage –0.3 to 4.2 DD-PLL1/2 DD-RTC DD-CPG Internal power supply voltage –0.3 to 2.5 Input voltage –0.3 to V + 0.3 –20 to 75, –40 to 85* °C Operating temperature...
Page 742: Dc Characteristics
23.2 DC Characteristics Table 23.2 DC Characteristics (HD6417750BP200M, HD6417750SBP200) (Ta = –20 to +75°C) Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC 1.95 2.07 Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 743 2. The current dissipation values are for V min = V – 0.5 V and V max = 0.5 V with all output pins unloaded. 3. I is the sum of the V , and V 3.3 V system currents. DD-PLL1/2 DD-RTC DD-CPG...
Page 744 Table 23.3 DC Characteristics (HD6417750F167) (cont) (Ta = –20 to +75°C) Item Symbol Unit Test Conditions Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: 1. Connect V , and V to V , and V , and V to GND, DD-PLL1/2...
Page 745 Table 23.4 DC Characteristics (HD6417750F167) (cont) (Ta = –20 to +75°C) Item Symbol Unit Test Conditions × 5(6(7, Input voltage — NMI, 7567 Other input — pins × 5(6(7, –0.3 — NMI, 7567 × Other input –0.3 — pins Output All output —...
Page 746 Table 23.5 DC Characteristics (HD6417750VF128, HD6417750SVF133) (cont) (Ta = –20 to +75 Item Symbol Unit Test Conditions Current Normal — — = 128 MHz/133 MHz dissipation operation Sleep mode — — Standby — — Ta = 25 C (RTC on* mode —...
Page 747: Ac Characteristics
Note: To protect chip reliability, do not exceed the output current values in table 23.3. 23.3 AC Characteristics In principle, SH7750 Series input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 23.7 Clock Timing (HD6417750BP200M, HD6417750SBP200)
Page 748 Table 23.9 Clock Timing (HD6417750SVF133) Item Symbol Unit Operating CPU, FPU, cache, TLB — — frequency External bus — — Peripheral modules — — Table 23.10 Clock Timing (HD6417750VF128) Item Symbol Unit Operating CPU, FPU, cache, TLB — frequency External bus —...
Page 749: Clock And Control Signal Timing
23.3.1 Clock and Control Signal Timing Table 23.11 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200) = 3.0 to 3.6 V, V = 1.8 V, T = –20 to +75°C, C = 30 pF) Item Symbol Unit Figure EXTAL PLL2 1/2 divider 66.7 clock input operating...
Page 750 Table 23.11 Clock and Control Signal Timing (HD6417750BP200M, HD6417750SBP200) (cont) = 3.0 to 3.6 V, V = 1.8 V, T = –20 to +75°C, C = 30 pF) Item Symbol Unit Figure µs PLL synchronization settling time — 23.9, 23.10 Standby return oscillation settling time 1 —...
Page 751 Table 23.12 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I, HD6417750SF167) (HD6417750F167: V = 3.0 to 3.6 V, V = 1.8 V, T = –20 to +75°C, C = 30 pF HD6417750F167I: V = 3.0 to 3.6 V, V = 1.8 V, T = –40 to +85°C, C = 30 pF) Item...
Page 752 Table 23.12 Clock and Control Signal Timing (HD6417750F167, HD6417750F671I, HD6417750SF167) (cont) (HD6417750F167: V = 3.0 to 3.6 V, V = 1.8 V, T = –20 to +75°C, C = 30 pF HD6417750F167I: V = 3.0 to 3.6 V, V = 1.8 V, T = –40 to +85°C, C = 30 pF) Item...
Page 753 Table 23.13 Clock and Control Signal Timing (HD6417750SVF133) = 3.0 to 3.6 V, V = 1.5 V, T = –20 to +75°C, C = 30 pF) Item Symbol Unit Figure EXTAL PLL2 1/2 divider 44.3 clock input operating operating frequency 1/2 divider not 22.2 operating...
Page 754 Table 23.13 Clock and Control Signal Timing (HD6417750SVF133) (cont) = 3.0 to 3.6 V, V = 1.5 V, T = –20 to +75°C, C = 30 pF) Item Symbol Unit Figure µs PLL synchronization settling time — 23.9, 23.10 Standby return oscillation settling time 1 —...
Page 755 Table 23.14 Clock and Control Signal Timing (HD6417750VF128) = 3.0 to 3.6 V, V = 1.5 V, T = –20 to +75°C, C = 30 pF) Item Symbol Unit Figure EXTAL PLL2 1/2 divider 43.0 clock input operating operating frequency 1/2 divider not 21.5 operating...
Page 756 Table 23.14 Clock and Control Signal Timing (HD6417750VF128) = 3.0 to 3.6 V, V = 1.5 V, T = –20 to +75°C, C = 30 pF) Item Symbol Unit Figure µs PLL synchronization settling time — 23.9, 23.10 Standby return oscillation settling time 1 —...
Page 757 CKOL1 CKOH1 1/2V 1/2V CKOf CKOr Figure 23.2(1) CKIO Clock Output Timing CKOH2 CKOL2 1.4 V 1.4 V 1.4 V Figure 23.2(2) CKIO Clock Output Timing Rev. 4.0, 04/00, page 749 of 850...
Page 758 Stable oscillation CKIO, internal clock RESW OSC1 RESET SCK2RH SCK2 OSCMD MDRH MD8, MD7, MD2–MD0 TRSTRH TRST Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating Figure 23.3 Power-On Oscillation Settling Time Standby Stable oscillation CKIO, internal clock RESW...
Page 759 Stable oscillation Internal clock RESW OSC1 RESET SCK2RH SCK2 OSCMD MDRH MD8, MD7, MD2–MD0 TRSTRH TRST CKIO Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 operating Figure 23.5 Power-On Oscillation Settling Time Stable oscillation Standby Internal clock RESW OSC2...
Page 760 Standby Stable oscillation CKIO, internal clock OSC3 Note: Oscillation settling time when on-chip resonator is used Figure 23.7 Standby Return Oscillation Settling Time (Return by NMI) Stable oscillation Standby CKIO, internal clock OSC4 – Note: Oscillation settling time when on-chip resonator is used Figure 23.8 Standby Return Oscillation Settling Time (Return by ,5/6 ,5/6–,5/3 ,5/3)
Page 761 Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input × 2 PLL synchronization PLL synchronization PLL output, CKIO output Internal clock STATUS1– Normal Standby Normal STATUS0 Note: When external clock from EXTAL is input Figure 23.9 PLL Synchronization Settling Time in Case of 5(6(7 5(6(7 or NMI Interrupt 5(6(7 5(6(7...
Page 762 CKIO RESW SCK2RS SCK2RH SCK2 Figure 23.11 Manual Reset Input Timing RESET MDRS MDRH MD6–MD3 Figure 23.12 Mode Input Timing Rev. 4.0, 04/00, page 754 of 850...
Page 763: Control Signal Timing
23.3.2 Control Signal Timing Table 23.15 Control Signal Timing HD6417750 F167 HD6417750 HD6417750 F167I BP200M HD6417750 HD6417750 HD6417750 HD6417750 VF128 SVF133 SF167 SBP200 64 MHz* 67 MHz* 83 MHz* 100 MHz* Item Symbol Min Unit Figure Note %5(4 setup — —...
Page 764 CKIO BREQS BREQH BREQS BREQH BACKH BACKH A[25-0], BOFF1 BON1 Figure 23.13 Control Signal Timing Normal operation Standby mode Normal operation CKIO STATUS 0, STATUS 1 Normal Standby Normal STD2 STD1 CSn, RD, RD/WR, WEn, BS, RAS, RAS2, CE2A, CE2B, RD2, BON2 BOFF2 RD/WR2...
Page 765: Bus Timing
23.3.3 Bus Timing Table 23.16 Bus Timing = 3.0 to 3.6 V, V = typ. 1.8 V, T = –20 to +75°C, C = 30 pF, PLL2 on) HD6417750 F167 HD6417750 HD6417750 F167I BP200M HD6417750 HD6417750 HD6417750 HD6417750 VF128 SVF133 SF167 SBP200 64 MHz*...
Page 766 Table 23.16 Bus Timing (cont) = 3.0 to 3.6 V, V = typ. 1.8 V, T = –20 to +75°C, C = 30 pF, PLL2 on) HD6417750 F167 HD6417750 HD6417750 F167I BP200M HD6417750 HD6417750 HD6417750 HD6417750 VF128 SVF133 SF167 SBP200 64 MHz* 67 MHz* 83 MHz*...
Page 767 CKIO A25 – A0 D63 – D0 (read) WED1 WEDF WEDF D63 – D0 (write) DACD DACD DACD DACKn (SA: IO ← memory) DACDF DACDF DACKn (SA: IO → memory) DACD DACD DACKn (DA) Note: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Page 768 CKIO A25 – A0 D63 – D0 (read) WED1 WEDF WEDF D63 – D0 (write) RDYS RDYH DACD DACD DACD DACKn (SA: IO ← memory) DACDF DACDF DACKn (SA: IO → memory) DACD DACD DACKn (DA) Note: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
Page 769 CKIO A25–A0 D63–D0 (read) WED1 WEDF WEDF D63–D0 (write) RDYS RDYH RDYS RDYH DACD DACD DACD DACKn (SA: IO ← memory) DACDF DACDF DACKn (SA: IO → memory) DACD DACD DACKn (DA) Note: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer Figure 23.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) Rev.
Page 770 CKIO – – (read) WED1 WEDF WEDF – (write) DACD DACD DACKn DACD (SA: IO ← memory) DACDF DACDF DACKn (SA: IO → memory) DACD DACD DACKn (DA) Figure 23.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev.
Page 771 CKIO A25–A5 A4–A0 D31–D0 (read) DACD DACD DACD DACKn (SA: IO ← memory) DACD DACD DACKn (DA) Note: IO: DACK device SA: Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high Figure 23.19 Burst ROM Bus Cycle (No Wait) Rev.
Page 772 Figure 23.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait) Rev. 4.0, 04/00, page 764 of 850...
Page 773 Figure 23.21 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev. 4.0, 04/00, page 765 of 850...
Page 774 Figure 23.22 Burst ROM Bus Cycle (One Internal Wait + One External Wait) Rev. 4.0, 04/00, page 766 of 850...
Page 775 Figure 23.23 Synchronous DRAM Auto-Precharge Bus Cycle: Single (RCD = 1, CAS Latency = 3, TPC = 3) Rev. 4.0, 04/00, page 767 of 850...
Page 776 Figure 23.24 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD = 1, CAS Latency = 3, TPC = 3) Rev. 4.0, 04/00, page 768 of 850...
Page 777 Tc4/Td1 CKIO BANK Precharge-sel Addr RASD RASD CASD2 CASD2 CASD2 DQMD DQMD DQMn D63–D0 (read) D63–D0 (write) DACD DACD DACD DACKn (SA: IO ← memory) Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD = 1, CAS Latency = 3) Rev.
Page 778 Tc4/Td1 CKIO BANK Precharge-sel Addr RASD RASD RASD RASD CASD2 CASD2 CASD2 DQMD DQMD DQMn D63–D0 (read) D63–D0 (write) DACD DACD DACD DACKn (SA: IO ← memory) Figure 23.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (TPC = 1, RCD = 1, CAS Latency = 3) Rev.
Page 779 Tc4/Td1 CKIO BANK Precharge-sel Addr RASD RASD CASD2 CASD2 DQMD DQMD DQMn D63–D0 (read) D63–D0 (write) DACD DACD DACD DACKn (SA: IO ← memory) Figure 23.27 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency = 3) Rev. 4.0, 04/00, page 771 of 850...
Page 780 Trwl Trwl CKIO BANK Precharge-sel Addr column RD/WR RASD RASD CASD2 CASD2 CASD2 CASS DQMD DQMD DQMn D63–D0 (write) DACD DACD DACKn (SA: IO → memory) Figure 23.28 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD = 1, TRWL = 2, TPC = 1) Rev.
Page 781 Trwl Trwl CKIO BANK Precharge-sel Addr RD/WR RASD RASD CASD2 CASD2 CASD2 CASS DQMD DQMD DQMn D63–D0 (write) DACD DACD DACKn (SA: IO → memory) Figure 23.29 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD = 1, TRWL = 2, TPC = 1) Rev.
Page 782 Trwl Trwl CKIO BANK Precharge-sel Addr RD/WR RASD RASD CASD2 CASD2 CASD2 CASS DQMD DQMD DQMn D63–D0 (write) DACD DACD DACKn (SA: IO → memory) Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands, Burst (RCD = 1, TRWL = 2) Rev.
Page 783 Trwl Trwl CKIO BANK Precharge-sel Addr RD/WR RASD RASD RASD RASD CASD2 CASD2 CASD2 CASS DQMD DQMD DQMn D63–D0 (write) DACD DACD DACD DACKn (SA: IO → memory) Figure 23.31 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE Commands, Burst (TPC = 1, RCD = 1, TRWL = 2) Rev.
Page 784 Trwl Trwl Tnop (Tnop) CKIO BANK Precharge-sel Addr RD/WR CASD2 CASD2 CASS DQMD DQMD DQMn D63–D0 (write) SA-DMA DACD DACD DACKn (SA: IO → memory) Normal write Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line.
Page 785 CKIO BANK Precharge-sel Addr RASD RASD CASD2 CASD2 DQMD DQMD DQMn D63–D0 (write) DACD DACD DACKn Figure 23.33 Synchronous DRAM Bus Cycle: Synchronous DRAM Precharge Command (TPC = 1) Rev. 4.0, 04/00, page 777 of 850...
Page 786 TRr1 TRr2 TRr3 TRr4 TRrw TRr5 CKIO BANK Precharge-sel Addr RASD RASD RASD RASD CASD2 CASD2 CASD2 CASD2 DQMD DQMD DQMn D63–D0 (write) DACD DACD DACKn Figure 23.34 Synchronous DRAM Bus Cycle: Synchronous DRAM Auto-Refresh (TRAS = 1, TRC = 1) Rev.
Page 787 TRs1 TRs2 TRs3 TRs4 TRs5 CKIO BANK Precharge-sel Addr RASD RASD RASD RASD CASD2 CASD2 CASD2 CASD2 DQMD DQMD DQMn D63–D0 (write) CKED CKED DACD DACD DACKn Figure 23.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh (TRC = 1) Rev. 4.0, 04/00, page 779 of 850...
Page 788 TMw4 TMw5 TRp1 TRp2 TRp3 TRp4 TMw2 TMw3 CKIO BANK Precharge-sel Addr RASD RASD RASD CASD2 CASD2 CASD2 CASD2 DQMD DQMD DQMn D63–D0 (write) (High) DACD DACD DACKn Figure 23.36 (a) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (PALL) Rev.
Page 789 TMw4 TMw5 TRp1 TRp2 TRp3 TRp4 TMw2 TMw3 CKIO BANK Precharge-sel Addr RASD RASD RASD CASD2 CASD2 CASD2 CASD2 DQMD DQMD DQMn D63–D0 (write) (High) DACD DACD DACKn Figure 23.36 (b) Synchronous DRAM Bus Cycle: Synchronous DRAM Mode Register Setting (SET) Rev.
Page 790 Figure 23.37 DRAM Bus Cycles ((1) RCD = 0, AnW = 0, TPC = 1; (2) RCD = 1, AnW = 1, TPC = 2) Rev. 4.0, 04/00, page 782 of 850...
Page 791 CKIO column A25–A0 RASD RASD RASD CASD1 CASD1 CASD1 D63–D0 (read) D63–D0 (write) DACD DACD DACKn (SA: IO ← memory) Figure 23.38 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) Rev. 4.0, 04/00, page 783 of 850...
Page 792 Figure 23.39 DRAM Burst Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1) Rev. 4.0, 04/00, page 784 of 850...
Page 793 Figure 23.40 DRAM Burst Bus Cycle (EDO Mode, RCD = 1, AnW = 1, TPC = 1) Rev. 4.0, 04/00, page 785 of 850...
Page 794 Figure 23.41 DRAM Burst Bus Cycle (EDO Mode, RCD = 1, AnW = 1, TPC = 1, 2-Cycle CAS Negate Pulse Width) Rev. 4.0, 04/00, page 786 of 850...
Page 795 Figure 23.42 DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode, RCD = 0, AnW = 0) Rev. 4.0, 04/00, page 787 of 850...
Page 796 Figure 23.43 DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev. 4.0, 04/00, page 788 of 850...
Page 797 Figure 23.44 DRAM Burst Bus Cycle (Fast Page Mode, RCD = 0, AnW = 0, TPC = 1) Rev. 4.0, 04/00, page 789 of 850...
Page 798 Figure 23.45 DRAM Burst Bus Cycle (Fast Page Mode, RCD = 1, AnW = 1, TPC = 1) Rev. 4.0, 04/00, page 790 of 850...
Page 799 Figure 23.46 DRAM Burst Bus Cycle (Fast Page Mode, RCD = 1, AnW = 1, TPC = 1, 2-Cycle CAS Negate Pulse Width) Rev. 4.0, 04/00, page 791 of 850...
Page 800 Figure 23.47 DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode, RCD = 0, AnW = 0) Rev. 4.0, 04/00, page 792 of 850...
Page 801 Figure 23.48 DRAM Burst Bus Cycle: RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev. 4.0, 04/00, page 793 of 850...
Page 802 TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 RASD RASD RASD CASD1 CASD1 CASD1 D63–D0 (write) DACD DACKn (SA: IO ← memory) DACD DACKn (SA: IO → memory) Figure 23.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS = 0, TRC = 1) Rev.
Page 803 TRr1 TRr2 TRr3 TRr4 TRr4w TRr5 CKIO A25–A0 RASD RASD RASD CASD1 CASD1 CASD1 D63–D0 (write) DACD DACKn (SA: IO ← memory) DACD DACKn (SA: IO → memory) Figure 23.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS = 1, TRC = 1) Rev.
Page 804 TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 RASD RASD RASD CASD1 CASD1 CASD1 D63–D0 (write) DACD DACKn (SA: IO ← memory) DACD DACKn (SA: IO → memory) Figure 23.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC = 1) Rev. 4.0, 04/00, page 796 of 850...
Page 805 Figure 23.52 (1) PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) (2) PCMCIA Memory Bus Cycle (TED = 1, TEH = 1, One Internal Wait + One External Wait) Rev. 4.0, 04/00, page 797 of 850...
Page 806 Figure 23.53 (1) PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) (2) PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Internal Wait + One External Wait) Rev. 4.0, 04/00, page 798 of 850...
Page 807 Figure 23.54 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Internal Wait, Bus Sizing) Rev. 4.0, 04/00, page 799 of 850...
Page 808 Figure 23.55 MPX Basic Bus Cycle: Read Rev. 4.0, 04/00, page 800 of 850...
Page 809 Figure 23.56 MPX Basic Bus Cycle: Write Rev. 4.0, 04/00, page 801 of 850...
Page 810 Figure 23.57 MPX Bus Cycle: Burst Read Rev. 4.0, 04/00, page 802 of 850...
Page 811 Figure 23.58 MPX Bus Cycle: Burst Write Rev. 4.0, 04/00, page 803 of 850...
Page 812 Figure 23.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait) Rev. 4.0, 04/00, page 804 of 850...
Page 813 CKIO A25–A0 D63–D0 (read) WED1 WED1 WEDF DACD DACD DACKn (SA: IO ← memory) DACD DACD DACKn (DA) Figure 23.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) Rev.
Page 814: Peripheral Module Signal Timing
23.3.4 Peripheral Module Signal Timing Table 23.17 Peripheral Module Signal Timing HD6417750 F167 HD6417750 HD6417750 F167I BP200M HD6417750 HD6417750 HD6417750 HD6417750 VF128 SVF133 SF167 SBP200 64 MHz* 67 MHz* 83 MHz* 100 MHz* Module Item Symbol Min Unit Figure TMU, Timer clock —...
Page 815 Table 23.17 Peripheral Module Signal Timing (cont) HD6417750 F167 HD6417750 HD6417750 F167I BP200M HD6417750 HD6417750 HD6417750 HD6417750 VF128 SVF133 SF167 SBP200 64 MHz* 67 MHz* 83 MHz* 100 MHz* Module Item Symbol Min Unit Figure Output data — — — —...
Page 816 Table 23.17 Peripheral Module Signal Timing (cont) HD6417750 F167 HD6417750 HD6417750 F167I BP200M HD6417750 HD6417750 HD6417750 HD6417750 VF128 SVF133 SF167 SBP200 64 MHz* 67 MHz* 83 MHz* 100 MHz* Module Item Symbol Min Unit Figure $6(%5. H-UDI — — — —...
Page 817 TCLK TCLKWH TCLKWL TCLKf TCLKr Figure 23.61 TCLK Input Timing Stable oscillation RTC internal clock V cc V cc min ROSC Figure 23.62 RTC Oscillation Settling Time at Power-On SCKW SCK, SCK2 Scyc SCKf SCKr Figure 23.63 SCK Input Clock Timing Rev.
Page 818 Scyc Figure 23.64 SCI I/O Synchronous Mode Clock Timing CKIO Ports 19–0 (read) PORTS PORTH PORTD PORTD Ports 19–0 (write) Figure 23.65 I/O Port Input/Output Timing CKIO DRQH DRQH DRQS DRQS DRAKD DRAKn Figure 23.66 '5(4 '5(4 '5(4/DRAK Timing '5(4 Rev.
Page 819 TCKcyc TCKL TCKH 1/2V 1/2V TCKf TCKr Note: When clock is input from TCK pin Figure 23.67 TCK Input Timing SCK2/ ASEBRKS ASEBRKH ASEBRKS ASEBRKH BRKACK Figure 23.68 Reset Hold Timing TCKcyc TDIS TDIH Figure 23.69 H-UDI Data Transfer Timing PINBRK Figure 23.70 Pin Break Timing Rev.
Page 820: Ac Characteristic Test Conditions
23.3.5 AC Characteristic Test Conditions The AC characteristic test conditions are as follows: • Input/output signal reference level: 1.5 V (V = 3.3 ±0.3 V) • Input pulse level: V for 5(6(7, 7567, NMI, and $6(%5./BRKACK) –3.0 V (V –V •...
Page 821: Delay Time Variation Due To Load Capacitance
23.3.6 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to the SH7750’s pins is shown below. The graph shown in figure 23.72 should be taken into consideration if the stipulated capacitance is exceeded when connecting an external device.
Page 822: Appendix A Address List
Appendix A Address List Table A.1 Address List Synchro- Area 7 Power-On Manual nization Module Register P4 Address Address* Size Reset Reset Sleep Standby Clock PTEH H'FF00 0000 H'1F00 0000 32 Undefined Undefined Held Held Iclk PTEL H'FF00 0004 H'1F00 0004 32 Undefined Undefined Held...
Page 823 Table A.1 Address List (cont) Synchro- Area 7 Power-On Manual nization Address* Reset Reset Clock Module Register P4 Address Size Sleep Standby H'FF80 0014 H'1F80 0014 32 H'0000 0000 Held Held Held Bclk H'FF80 0018 H'1F80 0018 16 H'0000 Held Held Held Bclk...
Page 824 Table A.1 Address List (cont) Synchro- Area 7 Power-On Manual nization Address* Reset Reset Clock Module Register P4 Address Size Sleep Standby FRQCR H'FFC0 0000 H'1FC0 0000 16 Held Held Held Pclk STBCR H'FFC0 0004 H'1FC0 0004 8 H'00 Held Held Held Pclk...
Page 825 Table A.1 Address List (cont) Synchro- Area 7 Power-On Manual nization Address* Reset Reset Clock Module Register P4 Address Size Sleep Standby TCR0 H'FFD8 0010 H'1FD8 0010 16 H'0000 H'0000 Held Held Pclk TCOR1 H'FFD8 0014 H'1FD8 0014 32 H'FFFF FFFF H'FFFF FFFF Held Held Pclk TCNT1...
Page 826 3. Use word-size access when writing. Perform the write with the upper byte set to H'5A or H'A5, respectively. Byte- and longword-size writes cannot be used. Use byte-size access when reading. 4. SH7750S only Rev. 4.0, 04/00, page 819 of 850...
Page 827: Appendix B Package Dimensions
2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 256 × φ0.75 ± 0.15 0.30 0.10 Details of the part A Hitachi Code BP-256 JEDEC Conforms EIAJ — Weight (reference value) 3.0 g...
Page 828 Unit: mm 30.6 ± 0.2 *0.22 ± 0.05 0.10 M 0.20 ± 0.04 1.25 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code FP-208E JEDEC — EIAJ Conforms *Dimension including the plating thickness Weight (reference value) 5.3 g Base material dimension Figure B.2 Package Dimensions (208-Pin QFP)
Page 829: Appendix C Mode Pin Settings
Appendix C Mode Pin Settings The MD8–MD0 pin values are input in the event of a power-on reset via the 5(6(7 or SCK2/05(6(7 pin. Clock Modes Initial Clock Frequency Pin Values Ratio* Peripheral Frequency Module Mode Divider 1 PLL1 PLL2 Clock Clock Clock...
Page 830 Area 0 Memory Type Pin Value Memory Type MPX bus Normal memory Master/Slave Pin Value Master/Slave Slave Master Clock Input Pin Value Clock Input External input clock Crystal resonator Rev. 4.0, 04/00, page 823 of 850...
Page 831: Appendix
Appendix D &.,25(1% Pin Configuration SH7750 Series VDDQ rd_pullup_control rd_dt_ rd_hiz_control VDDQ VDDQ rdwr_pullup_control rdwr_dt_ rdwr_hiz_control VDDQ PLL2 CKIO Bus clock ckio_hiz_control CKIO2 VDDQ VSSQ Figure D.1 &.,25(1% &.,25(1% Pin Configuration &.,25(1% &.,25(1% Rev. 4.0, 04/00, page 824 of 850...
Page 832 &.,25(1% &.,25(1% &.,25(1% &.,25(1% Description 5'5, RD/:55, and CKIO2 have the same pin states as 5', RD/:5, and CKIO, respectively 5'5, RD/:55, and CKIO2 are in the high-impedance state Note: CKIO is fed back to PLL2 to coordinate the external clock and internal clock phases. However, CKIO2 is not fed back.
Page 833: Appendix E Pin Functions
Appendix E Pin Functions Pin States Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State Reset Reset (Power-On) (Manual) Signal Name Master Slave Master Slave Sleep Standby Released Notes D0–D7 D8–D15 D16–D23 D24–D31 D32–D39 ZK * ZK * Output state held when...
Page 834 Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State (cont) Reset Reset (Power-On) (Manual) Signal Name Master Slave Master Slave Sleep Standby Released Notes :(:/&$6:/DQM7 O :(9/&$69/DQM6 O :(8/&$68/DQM5 O :(7/&$67/DQM4 O :(6/&$66/DQM3 O :(5/&$65/DQM2 O :(4/&$64/DQM1 O :(3/&$63/DQM0 O DACK1–DACK0 DMAC...
Page 835 Table E.1 Pin States in Reset, Power-Down State, and Bus-Released State (cont) Reset Reset (Power-On) (Manual) Signal Name Master Slave Master Slave Sleep Standby Released Notes H-UDI H-UDI H-UDI H-UDI 7567 H-UDI CKIO2* 5'5* RD/:55* &.,25(1% Notes: I: Input O: Output H: High-level output L: Low-level output Z: High-impedance...
Page 836: Handling Of Unused Pins
Handling of Unused Pins • When RTC is not used  EXTAL2: Pull up to 3.3 V  XTAL2: Leave unconnected  VDD-RTC: Power supply (3.3 V)  VSS-RTC: Power supply (0 V) • When PLL1 is not used  VDD-PLL1: Power supply (3.3 V) ...
Page 837: Appendix F Synchronous Dram Address Multiplexing Tables
Appendix F Synchronous DRAM Address Multiplexing Tables BUS 64 (16M: 512k × 16b × 2) × 4 AMX 0 AMXEXT 0 16M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address...
Page 838 BUS 32 (16M: 512k × 16b × 2) × 2 AMX 0 AMXEXT 0 16M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 839 BUS 64 (16M: 512k × 16b × 2) × 4 AMX 0 AMXEXT 1 16M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Not used Rev.
Page 840 BUS 32 (16M: 512k × 16b × 2) × 2 AMX 0 AMXEXT 1 16M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 841 BUS 64 (16M: 1M × 8b × 2) × 8 AMX 1 AMXEXT 0 16M, column-addr-9bit 16MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used...
Page 842 BUS 32 (16M: 1M × 8b × 2) × 4 AMX 1 AMXEXT 0 16M, column-addr-9bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 843 BUS 64 (16M: 1M × 8b × 2) × 8 AMX 1 AMXEXT 1 16M, column-addr-9bit 16MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used...
Page 844 BUS 32 (16M: 1M × 8b × 2) × 4 AMX 1 AMXEXT 1 16M, column-addr-9bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 845 BUS 64 (64M: 1M × 16b × 4) × 4 AMX 2 64M, column-addr-8bit 32MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Not used Rev.
Page 846 (10) BUS 32 (64M: 1M × 16b × 4) × 2 AMX 2 64M, column-addr-8bit 16MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 847 (11) BUS 64 (64M: 2M × 8b × 4) × 8 AMX 3 64M, column-addr-9bit 64MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Not used Rev.
Page 848 (12) BUS 32 (64M: 2M × 8b × 4) × 4 AMX 3 64M, column-addr-9bit 32MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 849 (13) BUS 64 (64M: 512k × 32b × 4) × 2 AMX 4 64M, column-addr-8bit 16MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Not used Rev.
Page 850 (14) BUS 32 (64M: 512k × 32b × 4) × 1 AMX 4 64M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 851 (15) BUS 64 (64M: 1M × 32b × 2) × 2 AMX 5 64M, column-addr-8bit 16MB SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Not used Rev.
Page 852 (16) BUS 32 (64M: 1M × 32b × 2) × 1 AMX 5 64M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 853 (17) BUS 32 (SH7750S only) AMX 6 column-addr-10bit 64MB AMXEXT 0 SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Rev. 4.0, 04/00, page 846 of 850...
Page 854 (18) BUS 32 (256M: 4M × 16b × 4) × 2 (SH7750S only) AMX 6 256M, column-addr-9bit 64MB AMXEXT 1 SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting...
Page 855 (19) BUS 64 (16M: 256k × 32b × 2) × 2 AMX 7 16M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used Not used Rev.
Page 856 (20) BUS 32 (16M: 256k × 32b × 2) × 1 AMX 7 16M, column-addr-8bit SH7750 Series Address Pins Synchronous DRAM Function Address Pins RAS Cycle CAS Cycle BANK selects bank address Address precharge setting Address Not used Not used...
Page 857: Appendix G Product Code Lineup
Appendix G Product Code Lineup Table G.1 SH7750 Series Product Code Lineup Operating Operating Abbreviation Voltage Frequency Temperature Mark Code Package SH7750 1.95 V 200 MHz –20 to 75°C HD6417750BP200M BGA-256 1.8 V 167 MHz –20 to 75°C HD6417750F167 QFP-208 –40 to 85°C...
Page 858 Publication Date: 1st Edition, August 1998 4th Edition, April 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

This manual is also suitable for:

Sh7750sSh7750

Hitachi SH7750 series Hardware Manual

Quick Links

Related Manuals for Hitachi SH7750 series

Summary of Contents for Hitachi SH7750 series