Figure 23.46 Dram Burst Bus Cycle: Ras Down Mode Continuation (Fast Page Mode, Rcd [1:0] = 00, Anw [2:0] = 000) - Hitachi SH7751 Hardware Manual

CKIO
Address
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.46 DRAM Burst Bus Cycle: RAS Down Mode Continuation
Rev. 3.0, 04/02, page 1002 of 1064
Tnop Tc1 Tc2
t
AD
c1
t
CASD1
t
RDS
d1
t
WDD
d1
t t
BSD BSD
t
DACD
t t
DACD DACD
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)
Tc1 Tc2
Tc1 Tc2
c2
t
CASD1
t
RDH
d2
t
WDD
d2
t
DACD
Tc1 Tc2
t
AD
c8
t
CSD
t
RWD
RAS down
t
RASD
mode ended
t t
CASD1 CASD1
t t
RDS RDH
d8
t
WDD
d8