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Table D.1
Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable,
Disable Common) (cont)
Pin Name
I/O
CKIO
O
STATUS1–STATUS0 O
–
I
NMI
I
DREQ1–DREQ0
I
DRAK1–DRAK0
O
MD0/SCK2
I/O
RXD
I
SCK
I/O
MD1/TXD2
I/O
MD2/RXD2
I
TxD
I/O
MD8/RTS2
I/O
TCLK
I/O
TDO
O
TMS
I
TCK
I
TDI
I
I
I
I
CA
I
Reset
(Power-On)
Master Slave
Master Slave
O
O
ZO*
O
O
O
14
PI
PI
I*
14
PI
PI
I*
13
PI
PI
I*
L
L
L
19
19
13
I*
I*
I*
13
PI
PI
I*
13
PI
PI
I*
19
19
13
I*
I*
Z*
19
19
13
I*
I*
I*
13
PZ
PZ
Z*
19
19
13
I*
I*
I*
13
PI
PI
I*
PO
PO
PO
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
14
PI
PI
I*
I
I
I
Reset
(Manual)
Standby
10
10
10
ZO*
ZO*
O
O
14
14
I*
I*
14
14
I*
I*
13
13
I*
I*
13
8
L
Z*
O*
13
13
I*
OI*
13
8
Z*
O*
13
13
I*
I*
13
13
13
I*
I*
Z*
O*
13
13
8
Z*
Z*
O*
13
13
I*
I*
13
13
8
O
Z*
O
Z*
O*
13
13
13
I*
I*
Z
8
O*
13
13
I*
I*
O
PO
PO
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
14
14
I*
I*
I
I
Rev. 3.0, 04/02, page 1045 of 1064
Hard-
Bus
ware
Released
Standby Notes
10
ZO*
Z
11
O
ZO*
14
I*
I
14
I*
I
13
I*
I
13
13
8
OI*
Z*
O*
Z
13
I*
O
Z
13
I*
I
8
13
I*
O
Z
13
Z*
O
Z
13
I*
I
O
Z
13
I*
O
Z
13
I*
O
Z
PO
Z
PI
I
PI
I
PI
I
PI
I
PI
I
14
I*
I
I
I
INTC
INTC
DMAC
DMAC
SCIF
SCI
SCI
SCIF
SCIF
SCI
SCIF
TMU
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
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