Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3) - Hitachi SH7751 Hardware Manual

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
Bit: 31
Initial value: 0
R/W: R
Bit: 23
Initial value: —
R/W: R/W
Bit: 15
Initial value: —
R/W: R/W
Bit: 7
Initial value: —
R/W: R/W
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 32-bit readable/writable registers
that specify the transfer count for the corresponding channel (byte count, word count, longword
count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while
H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the
remaining number of transfers is shown.
Bits 31–24 of these registers are reserved; they are always read as 0, and should only be written
with 0.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev. 3.0, 04/02, page 472 of 1064
30 29
0 0
R R
22 21
— —
R/W R/W
14 13
— —
R/W R/W
6 5
— —
R/W R/W
28 27
0 0
R R
20 19
— —
R/W R/W R/W
12 11
— —
R/W R/W R/W
4 3
— —
R/W R/W R/W
26 25 24
0 0
R R
18 17 16
— —
R/W R/W
10 9
— —
R/W R/W
2 1
— —
R/W R/W
0
R
—
8
—
0
—