Table of Contents
Advertisement
When an FPU operation instruction is executed, the FPU exception cause field is cleared to
zero first. When the next FPU exception is occurred, the corresponding bits in the FPU
exception cause field and FPU exception flag field are set to 1. The FPU exception flag field
holds the status of the exception generated after the field was last cleared.
RM: Rounding mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Bits 22 to 31: Reserved
These bits are always read as 0, and should only be written with 0.
6.3.3
Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL
register is a system register, and is accessed from the CPU side by means of LDS and STS
instructions. For example, to convert the integer stored in general register R1 to a single-precision
floating-point number, the processing flow is as follows:
R1
(LDS instruction)
6.4
Rounding
In a floating-point instruction, rounding is performed when generating the final operation result
from the intermediate result. Therefore, the result of combination instructions such as FMAC,
FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB,
or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL.
There are two rounding methods, the method to be used being determined by the RM field in
FPSCR.
RM = 00: Round to Nearest
RM = 01: Round to Zero
Round to Nearest: The operation result is rounded to the nearest expressible value. If there are
two nearest expressible values, the one with an LSB of 0 is selected.
If the unrounded value is 2
unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and
1023 and 53 for double-precision.
Rev. 3.0, 04/02, page 162 of 1064
FPUL
(single-precision FLOAT instruction)
Emax
–P
(2 – 2
) or more, the result will be infinity with the same sign as the
FR1
Advertisement
Table of Contents
