Table 7.8
System Control Instructions (cont)
Instruction
SETS
SETT
SLEEP
STC
SR,Rn
STC
GBR,Rn
STC
VBR,Rn
STC
SSR,Rn
STC
SPC,Rn
STC
SGR,Rn
STC
DBR,Rn
STC
Rm_BANK,Rn
STC.L
SR,@-Rn
STC.L
GBR,@-Rn
STC.L
VBR,@-Rn
STC.L
SSR,@-Rn
STC.L
SPC,@-Rn
STC.L
SGR,@-Rn
STC.L
DBR,@-Rn
STC.L
Rm_BANK,@-Rn
STS
MACH,Rn
STS
MACL,Rn
STS
PR,Rn
STS.L
MACH,@-Rn
STS.L
MACL,@-Rn
STS.L
PR,@-Rn
TRAPA
#imm
Rev. 3.0, 04/02, page 182 of 1064
Operation
1
S
1
T
Sleep or standby
SR
Rn
GBR
Rn
VBR
Rn
SSR
Rn
SPC
Rn
SGR
Rn
DBR
Rn
Rm_BANK
Rn (m = 0 to 7)
Rn – 4
Rn, SR
(Rn)
Rn – 4
Rn, GBR
(Rn)
Rn – 4
Rn, VBR
(Rn)
Rn – 4
Rn, SSR
(Rn)
Rn – 4
Rn, SPC
(Rn)
Rn – 4
Rn, SGR
(Rn)
Rn – 4
Rn, DBR
(Rn)
Rn – 4
Rn,
Rm_BANK
(Rn) (m = 0 to 7)
MACH
Rn
MACL
Rn
PR
Rn
Rn – 4
Rn, MACH
Rn – 4
Rn, MACL
Rn – 4
Rn, PR
(Rn)
PC + 2
SPC, SR
SSR,
#imm << 2
TRA,
H'160
EXPEVT,
VBR + H'0100
PC
Instruction Code
0000000001011000 —
0000000000011000 —
0000000000011011 Privileged
0000nnnn00000010 Privileged
0000nnnn00010010 —
0000nnnn00100010 Privileged
0000nnnn00110010 Privileged
0000nnnn01000010 Privileged
0000nnnn00111010 Privileged
0000nnnn11111010 Privileged
0000nnnn1mmm0010 Privileged
0100nnnn00000011 Privileged
0100nnnn00010011 —
0100nnnn00100011 Privileged
0100nnnn00110011 Privileged
0100nnnn01000011 Privileged
0100nnnn00110010 Privileged
0100nnnn11110010 Privileged
0100nnnn1mmm0011 Privileged
0000nnnn00001010 —
0000nnnn00011010 —
0000nnnn00101010 —
(Rn)
0100nnnn00000010 —
(Rn)
0100nnnn00010010 —
0100nnnn00100010 —
11000011iiiiiiii —
Privileged
T Bit
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—