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1.2
Block Diagram
Figure 1.1 shows an internal block diagram of the SH7751 Series.
I cache
CPG
INTC
SCI
(SCIF)
RTC
TMU
PCIC
(PCI)DMAC
32-bit
PCI
address/
data
Figure 1.1 Block Diagram of SH7751 Series Functions
Rev. 3.0, 04/02, page 10 of 1064
CPU
UBC
Lower 32-bit data
Cache and
ITLB
TLB
controller
BSC
External (SH) bus
interface
26-bit
SH bus
address
FPU
UTLB
O cache
DMAC
BSC:
Bus state controller
CPG:
Clock pulse generator
DMAC: Direct memory access controller
FPU:
Floating-point unit
INTC:
Interrupt controller
ITLB:
Instruction TLB (translation lookaside buffer)
UTLB: Unified TLB (translation lookaside buffer)
RTC:
Realtime clock
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
TMU:
Timer unit
32-bit
UBC:
User break controller
SH bus
PCIC:
PCI bus controller
data
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