Packet Process Card 3 (Ppc3) Description; Interoperability; Packet Processor Card (Ppc) Description - Cisco ASR 5000 series Installation And Administration Manual

ASR 5000 Hardware Platform Overview

Packet Process Card 3 (PPC3) Description

The PSC3 Packet Services Card application card is used with the System Management Card (SMC) to provide packet
processing and forwarding capabilities within an ASR 5000 system. The PSC3 provides increased aggregate throughput
and performance and a higher number of subscriber sessions than other ASR 5000 packet processing cards.
To optimize network efficiency and minimize down time, the system supports 1:n redundancy for PSC3s. If Session
Recovery is enabled, the minimum number of PSC3s per chassis increases from one to four cards. Three PSC3 cards are
active and one PSC3 is standby (redundant). This minimum configuration protects against software failures only. In
addition to increased hardware requirements, Session Recovery may reduce subscriber session capacity, performance,
and data throughput.
In the event of PSC3 card failure, tasks are migrated from the active PSC3 to the standby card. The line card installed
behind the PSC3 that was formerly active maintains the interfaces to the external network equipment. Installed
Redundancy Crossbar Cards (RCCs) provide a path for signaling and data traffic between the line card and the now
active packet processing card.

Interoperability

Do not mix PSC3s with PSCs, PSC2s. or PPCs, since this prevents the PSC3 from operating at its full potential. Due to
the different processor speeds and memory configurations, the PSC3 cannot be combined in a chassis with other packet
processing card types.

Packet Processor Card (PPC) Description

The PPC has features a quad-core x86 2.5Ghz CPU and 16GB of RAM. The processor runs a single copy of the
operating system. To check the CPU in the CLI, use the show cpu table command. The operating system running on the
PPC treats the dual-core processor as a 2-way multi-processor. You can see this in the output of the show cpu info
verbose command.
A second-generation data transport fixed programmable gate array (DT2 FPGA, abbreviated as DT2) connects the
PPC's NPU bus to the switch fabric interface. The FPGA also provides a bypass path between the line card or
Redundancy Crossbar Card (RCC) and the switch fabric for ATM traffic. Traffic from the line cards or the RCC is
received over the FPGA's serial links and is sent to the NPU on its switch fabric interface. The traffic destined for the
line cards or RCC is diverted from the NPU interface and sent over the serial links.
DT2 FPGA also connects to the control processors subsystem via a PCI-E bus. The PCI-E interface allows the control
processors to perform register accesses to the FPGA and some components attached to it, and also allows DMA
operations between the NPU and the control processors' memory. A statistics engine is provided in the FPGA. Two
reduced latency DRAM (RLDRAM) chips attached to the FPGA provide 64MB of storage for counters.
The PPC has a 2.5 G/bps-based security processor that provides the highest performance for cryptographic acceleration
of next-generation IP Security (IPsec), Secure Sockets Layer (SSL) and wireless LAN/WAN security applications with
the latest security algorithms.
OL-24878-01
Cisco ASR 5000 Series Aggregation Services Router Installation and Administration Guide ▄
ASR 5000 Application Cards ▀