Packet Processor Card (Ppc) Description - Cisco ASR 5000 series Product Overview

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Packet Processor Card (PPC) Description

The PPC has features a quad-core x86 2.5Ghz CPU and 16GB of RAM. The processor runs a single copy of the

operating system. To check the CPU in the CLI, use the show cpu table command. The operating system running on the

PPC treats the dual-core processor as a 2-way multi-processor. You can see this in the output of the show cpu info

verbose command.

A second-generation data transport fixed programmable gate array (DT2 FPGA, abbreviated as DT2) connects the

PPC's NPU bus to the switch fabric interface. The FPGA also provides a bypass path between the line card or

Redundancy Crossbar Card (RCC) and the switch fabric for ATM traffic. Traffic from the line cards or the RCC is

received over the FPGA's serial links and is sent to the NPU on its switch fabric interface. The traffic destined for the

line cards or RCC is diverted from the NPU interface and sent over the serial links.

DT2 FPGA also connects to the control processors subsystem via a PCI-E bus. The PCI-E interface allows the control

processors to perform register accesses to the FPGA and some components attached to it, and also allows DMA

operations between the NPU and the control processors' memory. A statistics engine is provided in the FPGA. Two

reduced latency DRAM (RLDRAM) chips attached to the FPGA provide 64MB of storage for counters.

The PPC has a 2.5 G/bps-based security processor that provides the highest performance for cryptographic acceleration

of next-generation IP Security (IPsec), Secure Sockets Layer (SSL) and wireless LAN/WAN security applications with

the latest security algorithms.

The PPC is fully redundant with a spare PPC.

3 million SAU and 6 million PDP contexts

2 million PDSN sessions

6 million HA sessions

Power Estimate

325W Maximum

The front panel of the PPC and its major components is shown below:

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