Emi Data Write Register Empty (Edwe)—Bit 12 - Motorola DSP56009 User Manual

External Memory Interface
EMI Programming Model
on page 4-26, Table 4-15 on page 4-29, and Table 4-16 on page 4-31, always starting
at A0 and ignoring the relative addressing extension bits.
The memory-wrap interrupt is generated when the significant bits in EBARx change
from all 1s to all 0s following the EBARx post-increment, for any particular selection
of addressing mode, word length, and bus width. For example, it can be seen from
Table 4-16 that for a selection of EAM[3:0] = 1101 there are 18 significant bits in
EBARx (A[17:0]) that determine the word address, therefore, in this case an EBARx
memory-wrap interrupt is generated when the 18 Least Significant Bits (LSBs) in
EBARx change from all 1s to all 0s as a result of the EBARx post-increment operation.
Similarly, for a selection of EAM[3:0] = 0101, EWL[2:0] = 001 and EBW = 0 there are
16 significant bits in EBARx (A[15:0]) that determine the word address.
Note: When EINR and EINW bits are cleared, memory-wrap interrupts cannot be
generated since no EBARx is post-incremented. EMWIE is cleared by
hardware or software reset.
4.2.7.8 EMI Data Write Register Empty (EDWE)—Bit 12
The EMI Data Write Register Empty (EDWE) read-only status bit indicates the state
of the EDWR. EDWE is set (EDWR empty) by the EMI controller when transferring a
data word from the EDWR to the EDBR during a memory write operation. EDWE is
cleared (EDWR full) when data is written into the EDWR when starting a memory
write operation.
Note: EDWE is set by hardware reset, software reset, individual reset, and while the
device is in the Stop state.
4.2.7.9 EMI Data Read Register Full (EDRF)—Bit 13
The EMI Data Read Register Full (EDRF) read-only status bit indicates the state of the
EDRR. EDRF is set (EDRR full) by the EMI controller when transferring a data word
from the EDRB to the EDRR at the end of a memory read operation.
Note: EDRF is cleared (EDRR empty) when EDRR is read by the DSP core.EDRF is
also cleared by hardware reset, software reset, individual reset, and while the
device is in the Stop state.
4.2.7.10 EMI Data Register Buffer and Data Read Register Full
(EBDF)—Bit 14
The EMI data register Buffer and Data read register Full (EBDF) read-only status bit
indicates the status of the EDRB and EDRR during read operations. EBDF is set when
both the EDRB and the EDRR contain data after memory read operations. EBDF is
cleared otherwise.
Note: EBDF is cleared by hardware reset, software reset, individual reset, and while
the DSP is in the Stop state.
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