Hitachi H8S/2646 Hardware Manual page 452

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

WDT0 TCSR Bit 3—Reserved Bit: It is always read as 1 and cannot be modified.

WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal

reset request and an NMI request when the TCNT overflows during the watchdog timer mode.

NMI request.

Internal reset request.

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources, obtained by dividing the system clock (ø) or subclock (ø SUB), for input to TCNT.

WDT0 Input Clock Select

Note: * An overflow period is the time interval between the start of counting up from H'00 on the

TCNT and the occurrence of a TCNT overflow.

Overflow Period* (where ø = 20 MHz)

ø/2 (initial value)

(Initial value)