Hitachi H8S/2646 Hardware Manual page 185

Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.
Bit 3 Bit 2 Bit 1
AE3 AE2 AE1
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: * In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.
In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to
1.
Bit 0
AE0 Description
0 A8–A23 address output disabled
1 A8 address output enabled; A9–A23 address output disabled
0 A8, A9 address output enabled; A10–A23 address output
disabled
1 A8–A10 address output enabled; A11–A23 address output
disabled
0 A8–A11 address output enabled; A12–A23 address output
disabled
1 A8–A12 address output enabled; A13–A23 address output
disabled
0 A8–A13 address output enabled; A14–A23 address output
disabled
1 A8–A14 address output enabled; A15–A23 address output
disabled
0 A8–A15 address output enabled; A16–A23 address output
disabled
1 A8–A16 address output enabled; A17–A23 address output
disabled
0 A8–A17 address output enabled; A18–A23 address output
disabled
1 A8–A18 address output enabled; A19–A23 address output
disabled
0 A8–A19 address output enabled; A20–A23 address output
disabled
1 A8–A20 address output enabled; A21–A23 address output
disabled
0 A8–A21 address output enabled; A22, A23 address output
disabled
1 A8–A23 address output enabled
(Initial value*)
(Initial value*)
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