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9.11.2
Register Configuration
Table 9-22 shows the port D register configuration.
Table 9-22 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit
:
7
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value :
0
R/W
:
W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port D Data Register (PDDR)
Bit
:
7
PD7DR
Initial value :
0
R/W
:
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
272
Abbreviation
PDDDR
PDDR
PORTD
PDPCR
6
5
0
0
W
W
6
5
PD6DR
PD5DR
PD4DR
0
0
R/W
R/W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
4
3
0
0
W
W
4
3
PD3DR
PD2DR
0
0
R/W
R/W
R/W
Address*
H'FE3C
H'FF0C
H'FFBC
H'FE43
2
1
0
0
W
W
W
2
1
PD1DR
PD0DR
0
0
R/W
R/W
0
0
0
0
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