Operation; Pwm Channel 1 Operation - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Operation

PWM waveforms are output from pins PWM1A to PWM1H as shown in figure 17-10.

Initial Settings: Set the PWM output polarity in PWPR1; enable the pins for PWM output with

PWOCR1; select the clock to be input to PWCNT1 with bits CKS2 to CKS0 in PWCR1; set the

PWM conversion cycle in PWCYR1; and set the first frame of data in PWBFR1A, PWBFR1C,

PWBFR1E, and PWBFR1G.

Activation: When the CST bit in PWCR1 is set to 1, a compare match between PWCNT1 and

PWCYR1 is generated. Data is transferred from PWBFR1A to PWDTR1A, from PWBFR1C to

PWDTR1C, from PWBFR1E to PWDTR1E, and from PWBFR1G to PWDTR1G. PWCNT1

starts counting up. At the same time the CMF bit in PWCR1 is set, so that, if the IE bit in PWCR1

has been set, an interrupt can be requested or the DTC can be activated.

Waveform Output: The PWM outputs selected by the OTS bits in PWDTR1A/C/E/G go high

when a compare match occurs between PWCNT1 and PWCYR1. The PWM outputs not selected

by the OTS bits are low. When a compare match occurs between PWCNT1 and

PWDTR1A/C/E/G, the corresponding PWM output goes low. If the corresponding bit in PWPR1

is set to 1, the output is inverted.

OTS (PWDTR1A) = 0

Next Frame: When a compare match occurs between PWCNT1 and PWCYR1, data is transferred

from PWBFR1A to PWDTR1A, from PWBFR1C to PWDTR1C, from PWBFR1E to PWDTR1E,

and from PWBFR1G to PWDTR1G. PWCNT1 is reset and starts counting up from H'000. The

CMF bit in PWCR1 is set, and if the IE bit in PWCR1 has been set, an interrupt can be requested

or the DTC can be activated.

OTS (PWDTR1A) = 1

Figure 17-10 PWM Channel 1 Operation

OTS (PWDTR1A) = 0

OTS (PWDTR1A) = 1