Table of Contents
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Table 1-1
Overview
Item
CPU
Bus controller
PC break controller •
Data transfer
controller (DTC)
16-bit timer pulse
unit (TPU)
Programmable
pulse generator
(PPG)
2
Specification
•
General-register machine
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
•
High-speed operation suitable for realtime control
Maximum clock rate: 20 MHz
High-speed arithmetic operations
8/16/32-bit register-register add/subtract : 50 ns
16 × 16-bit register-register multiply
16 × 16 + 42-bit multiply and accumulate : 200 ns
32 ÷ 16-bit register-register divide
•
Instruction set suitable for high-speed operation
Sixty-nine basic instructions
8/16/32-bit move/arithmetic and logic instructions
Unsigned/signed multiply and divide instructions
Multiply-and accumulate instruction
Powerful bit-manipulation instructions
•
Two CPU operating modes
Normal mode: 64-kbyte address space (not used on this device)
Advanced mode: 16-Mbyte address space
•
Address space divided into 8 areas, with bus specifications settable
independently for each area
•
Choice of 8-bit or 16-bit access space for each area
•
2-state or 3-state access space can be designated for each area
•
Number of program wait states can be set for each area
•
Direct connection to burst ROM supported
Supports debugging functions by means of PC break interrupts
•
Two break channels
•
Can be activated by internal interrupt or software
•
Multiple transfers or multiple types of transfer possible for one activation
source
•
Transfer possible in repeat mode, block transfer mode, etc.
•
Request can be sent to CPU for interrupt that activated DTC
•
6-channel 16-bit timer on-chip
•
Pulse I/O processing capability for up to 16 pins'
•
Automatic 2-phase encoder count capability
•
Maximum 8-bit pulse output possible with TPU as time base
•
Output trigger selectable in 4-bit groups
•
Non-overlap margin can be set
•
Direct output or inverse output setting possible
: 200 ns
: 1000 ns
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