Hitachi H8S/2646 Hardware Manual page 19

Section 5 Interrupt Controller ..........................................................................101
5.1 Overview............................................................................................................................ 101
5.1.1 Features ................................................................................................................. 101
5.1.2 Block Diagram...................................................................................................... 102
5.1.3 Pin Configuration.................................................................................................. 103
5.1.4 Register Configuration.......................................................................................... 103
5.2 Register Descriptions ......................................................................................................... 104
5.2.1 System Control Register (SYSCR)....................................................................... 104
5.2.2 Interrupt Priority Registers A to H, J, K, M
(IPRA to IPRH, IPRJ, IPRK, IPRM).................................................................... 105
5.2.3 IRQ Enable Register (IER) ................................................................................... 106
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 107
5.2.5 IRQ Status Register (ISR) .................................................................................... 108
5.3 Interrupt Sources................................................................................................................ 109
5.3.1 External Interrupts ................................................................................................ 109
5.3.2 Internal Interrupts ................................................................................................. 110
5.3.3 Interrupt Exception Handling Vector Table ......................................................... 110
5.4 Interrupt Operation............................................................................................................. 114
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 114
5.4.2 Interrupt Control Mode 0...................................................................................... 117
5.4.3 Interrupt Control Mode 2...................................................................................... 119
5.4.4 Interrupt Exception Handling Sequence ............................................................... 121
5.4.5 Interrupt Response Times ..................................................................................... 122
5.5 Usage Notes ....................................................................................................................... 123
5.5.1 Contention between Interrupt Generation and Disabling ..................................... 123
5.5.2 Instructions that Disable Interrupts....................................................................... 124
5.5.3 Times when Interrupts are Disabled ..................................................................... 124
5.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... 125
5.5.5 IRQ Interrupts ....................................................................................................... 125
5.6 DTC Activation by Interrupt.............................................................................................. 125
5.6.1 Overview............................................................................................................... 125
5.6.2 Block Diagram...................................................................................................... 125
5.6.3 Operation .............................................................................................................. 126
Section 6 PC Break Controller (PBC)..............................................................129
6.1 Overview............................................................................................................................ 129
6.1.1 Features ................................................................................................................. 129
6.1.2 Block Diagram...................................................................................................... 130
6.1.3 Register Configuration.......................................................................................... 131
6.2 Register Descriptions ......................................................................................................... 131
6.2.1 Break Address Register A (BARA)...................................................................... 131
6.2.2 Break Address Register B (BARB) ...................................................................... 132
iii