Hitachi H8S/2646 Hardware Manual page 447

WOVI1
(Interrupt request signal)
Internal NMI
Interrupt request signal
Internal reset signal*
Legend:
Timer control/status register
TCSR :
Timer counter
TCNT :
Note: * An internal reset signal can be generated by setting the register.
Interrupt
control
Overflow
Reset
control
TCNT
Module bus
Figure 12-1 (b) Block Diagram of WDT1
Clock
Clock
select
Internal clock
TCSR
WDT
ø/2
øSUB/2
ø/64
øSUB/4
ø/128
øSUB/8
ø/512
øSUB/16
ø/2048
øSUB/32
ø/8192
øSUB/64
ø/32768
øSUB/128
ø/131072
øSUB/256
Bus
interface
415