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3.16.3.13 EPx_STATUS Register (x: 0 to 7)
bit Symbol
EP0_STATUS
(0790H)
Read/Write
After reset
bit Symbol
EP1_STATUS
Read/Write
(0791H)
After reset
bit Symbol
EP2_STATUS
(0792H)
Read/Write
After reset
EP3_STATUS
bit Symbol
(0793H)
Read/Write
After reset
bit Symbol
EP4_STATUS
(0794H)
Read/Write
After reset
EP5_STATUS
bit Symbol
(0795H)
Read/Write
After reset
bit Symbol
EP6_STATUS
(0796H)
Read/Write
After reset
bit Symbol
EP7_STATUS
Read/Write
(0797H)
After reset
Note: EP4, 5, 6 and 7_STATUS registers are not used TMP92CZ26A.
TOGGLE Bit (Bit6)
0: TOGGLE
1: TOGGLE
SUSPEND (Bit5)
0: RESUME
1: SUSPEND
These registers are status registers for each endpoint. The <SUSPEND> is common
for all endpoint.
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
7
6
TOGGLE
R
0
Bit0
Bit1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
5
4
SUSPEND
STATUS[2]
STATUS[1]
R
R
0
1
This bit shows status of toggle sequence bit.
This bit shows status of power management of UDC.
In the SUSPEND status, some limitation about accessing to
UDC is needed.
For the detail, refer 3.10.9.
92CZ26A-390
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
3
2
1
STATUS[0]
FIFO_DISABLE
R
R
R
1
1
0
TMP92CZ26A
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
0
STAGE_ERR
R
0
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