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bit Symbol
ADREGSPL
(12B0H)
Read/Write
After reset
Function
bit Symbol
ADREGSPH
(12B1H)
Read/Write
After reset
Function
Channel X conversion result
•
Bits 5 ∼ 2 are always read as "0".
•
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to "1".
When Lower register (ADRECxL) is read, this bit is cleared to "0".
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to "1" if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to "0" by reading Flag.
High-priority AD Conversion Result Register SP Low
7
6
ADRSP1
ADRSP0
R
0
0
Store Lower 2 bits of an
AD conversion result
High-priority AD Conversion Result Register SP High
7
6
ADRSP9
ADRSP8
ADRSP7
0
0
Store Upper 8 bits of an AD conversion result
9
8
7
ADREGxH
7
6
5
Figure 3.23.9 AD Conversion Registers
92CZ26A-603
5
4
3
5
4
3
ADRSP6
ADRSP5
R
0
0
0
6
5
4
3
2
1
4
3
2
1
0
7
TMP92CZ26A
2
1
OVSRP
ADRSPRF
R
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
ADRSP4
ADRSP3
ADRSP2
0
0
0
ADREGxL
6
5
4
3
2
1
0
0
R
0
0
0
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