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Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to
TB0IN0pin
Main setting
← X
TB0MOD
X
← X
TB0FFCR
X
←
PPFC
–
1
← X
INTE56
1
← X
INTETB0
0
←
TB0RUN
–
0
Setting in INT6 routine
← TB0CP0 + 3ms/φT1
TB0RG0
← TB0RG0 + 2ms/φT1
TB0RG1
← X
TB0FFCR
X
← X
INTETB0
1
Setting in INTTB01 routine
← X
TB0FFCR
X
← X
INTETB0
0
X: Don't care, −: No change
When delay time is unnecessary, invert timer flip-flop TB0FF0 when the up counter
value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c)
plus the one –shot pulse width (p) to TB0RG1H/L when the interrupt INT6 occurs.
The TB0FF0 inversion should be enabled when the up counter (UC10) value matched
TB0RG1H/L, and disabled when generating the interrupt INTTB01.
*Clock state
1
0
1
0
0
1
0
0
0
0
1
0
–
–
–
–
–
X
0
0
X
–
–
–
0
0
X
0
0
0
X
X
–
1
X
1
–
–
1
1
–
–
0
0
X
0
0
0
–
–
0
0
–
–
0
0
X
0
0
0
92CZ26A-312
System clock :
f
SYS
Prescaler clock :
f
/4
SYS
Free-running
Count with φT1
Load to TB0CP0H/L at the rising edge of TB0IN0
Clear TB0FF0 to "0"
Disable TB0FF0 inversion
Select PP6 as TB0OUT0 pin (port setting)
Enable INT6
Disable INTTB00, INTTB01
Start TMRB0
Enable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
Enable INTTB01
Disable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
Disable INTTB01
TMP92CZ26A
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