2.12 EMAC Instruction Execution Times
Opcode
<EA>
muls.w
<ea>y, Dx
mulu.w
<ea>y, Dx
muls.l
<ea>y, Dx
mulu.l
<ea>y, Dx
mac.w
Ry, Rx, Raccx
mac.l
Ry, Rx, Raccx
msac.w
Ry, Rx, Raccx
msac.l
Ry, Rx, Raccx
mac.w
Ry, Rx, <ea>, Rw,
Raccx
mac.l
Ry, Rx, <ea>, Rw,
Raccx
msac.w
Ry, Rx, <ea>, Rw
msac.l
Ry, Rx, <ea>, Rw,
Raccx
mov.l
<ea>y, Raccx
mov.l
Raccy,Raccx
mov.l
<ea>y, MACSR
mov.l
<ea>y, Rmask
mov.l
<ea>y,Raccext01
mov.l
<ea>y,Raccext23
mov.l
Raccx,<ea>x
mov.l
MACSR,<ea>x
mov.l
Rmask, <ea>x
mov.l
Raccext01,<ea.x
mov.l
Raccext23,<ea>x
1
Effective address of (d16,PC) not supported
2
Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional
rounding is performed (MACSR[7:4] = 1---, -11-, --11)
MOTOROLA
Table 2-16. EMAC Instruction Execution Times
Rn
(An)
4(0/0)
6(1/0)
4(0/0)
6(1/0)
4(0/0)
6(1/0)
4(0/0)
6(1/0)
1(0/0)
—
1(0/0)
—
1(0/0)
—
1(0/0)
—
—
2(1/0)
—
2(1/0)
—
2(1/0)
—
2(1/0)
1(0/0)
—
1(0/0)
—
5(0/0)
—
4(0/0)
—
1(0/0)
—
1(0/0)
—
2
1(0/0)
—
1(0/0)
—
1(0/0)
—
1(0/0)
—
1(0/0)
—
Chapter 2. ColdFire Core
EMAC Instruction Execution Times
Effective Address
(An)+
-(An)
(d16,An)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
6(1/0)
—
—
—
—
—
—
—
—
—
—
—
—
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(d8,An,X
xxx.wl
n*SF)
7(1/0)
6(1/0)
7(1/0)
6(1/0)
—
—
—
—
—
—
—
—
—
—
—
—
1
—
—
1
—
—
1
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
#xxx
4(1/0)
4(1/0)
—
—
—
—
—
—
—
—
—
—
1(0/0)
—
5(0/0)
4(0/0)
1(0/0)
1(0/0)
—
—
—
—
—
2-27