Instruction Execution Timing; Timing Assumptions - Motorola ColdFire MCF5281 User Manual

Table 2-9. D1 Local Memory Hardware Configuration
Bits Name
7–4 RAM1SIZ RAM bank 1size.
0x0–0x3 No RAM.
0100 4KB RAM.
0101 8KB RAM.
0110 16KB RAM.
0111 32KB RAM.
1000 64KB RAM. (This is the value used for MCF5282)
1001 128KB RAM.
0xA–0xF Reserved.
3–0 ROM1SIZ ROM bank 1size.
0x0–0x3 No ROM. (This is the value used for MCF5282)
0100 4KB ROM.
0101 8KB ROM.
0110 16KB ROM.
0111 32KB ROM.
1000 64KB ROM.
1001 128KB ROM.
0xA–0xF Reserved.
2.8

Instruction Execution Timing

This section presents V2 processor instruction execution times in terms of processor core
clock cycles. The number of operand references for each instruction is enclosed in
parentheses following the number of processor clock cycles. Each timing entry is presented
as C(R/W) where:
• C is the number of processor clock cycles, including all applicable operand fetches
and writes, and all internal core cycles required to complete the instruction
execution.
• R/W is the number of operand reads (R) and writes (W) required by the instruction.
An operation performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time
details.
2.8.1

Timing Assumptions

For the timing data presented in this section, the following assumptions apply:
1. The operand execution pipeline (OEP) is loaded with the opword and all required
extension words at the beginning of each instruction execution. This implies that the
OEP does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or
extension words.
MOTOROLA
Information Field Description (continued)
Chapter 2. ColdFire Core
Instruction Execution Timing
Description
2-21