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10.3.5 Interrupt Acknowledge Level and Priority
Register (IACKLPRn)
Each time an IACK is performed, the interrupt controller responds with the vector number
of the highest priority source within the level being acknowledged. In addition to providing
the vector number directly for the byte-sized IACK read, this 8-bit register is also loaded
with information about the interrupt level and priority being acknowledged. This register
provides the association between the acknowledged "physical" interrupt request number
and the programmed interrupt level/priority. The contents of this read-only register are
described in Figure 10-8 and Table 10-11.
Field
Reset
R/W
Address
Figure 10-8. IACK Level and Priority Register (IACKLPRn)
Bits
Name
7
—
Reserved
6–4
LEVEL Interrupt level. Represents the interrupt level currently being acknowledged.
3–0
PRI
Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being
acknowledged.
0 Priority 0
1 Priority 1
2 Priority 2
3 Priority 3
4 Priority 4
5 Priority 5
6 Priority 6
7 Priority 7
8 Mid-Point Priority associated with the fixed level interrupts only
10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63))
Each ICRnx specifies the interrupt level (1-7) and the priority within the level (0-7). All
ICRnx registers can be read, but only ICRn8 to ICRn63 can be written. It is software's
responsibility to program the ICRnx registers with unique and non-overlapping level and
priority definitions. Failure to program the ICRnx registers in this manner can result in
undefined behavior. If a specific interrupt request is completely unused, the ICRnx value
can remain in its reset (and disabled) state.
MOTOROLA
7
6
—
LEVEL
IPSBAR + 0xC19, 0xD19
Table 10-11. IACKLPRn Field Descriptions
Chapter 10. Interrupt Controller Modules
4
3
PRI
0000_0000
R
Description
Register Descriptions
0
10-11
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