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Functional Description
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus
cycle to complete (5, 6) for an external reset request, the cycle is terminated. The reset
status bits are latched (7) and reset processing waits for the external RSTI pin to negate (8).
If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset
sequence continues after a PLL lock (9, 9A).
28.5.3.2 Reset Status Flags
For a POR reset, the POR and LVD bits in the RSR are set, and the SOFT, WDR, EXT,
LOC, and LOL bits are cleared even if another type of reset condition is detected during the
reset sequence for the POR.
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus
cycle to complete (5, 6) for an external reset request, the EXT, SOFT, and/or WDR bits
along with the LOC and/or LOL bits are set.
If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset sequence with no
other reset conditions detected, only the EXT, SOFT, and/or WDR bits are set.
If the RSR bits are latched (4) during the internal reset sequence with the RSTI pin not
asserted and no SOFT or WDR event, then the LOC and/or LOL bits are the only bits set.
For a LVD reset, the LVD bit in the RSR is set, and the SOFT, WDR, EXT, LOC, and LOL
bits are cleared to 0 even if another type of reset condition is detected during the reset
sequence for LVD.
MOTOROLA
Chapter 28. Reset Controller Module
28-11
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