Dram Address And Control Register (Dacrn); Dacrn Field Descriptions - Motorola ColdFire MCF5281 User Manual

SDRAM Controller Operation
15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1)
The DACRn registers, shown in Figure 15-3, contain the base address compare value and
the control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing
are also controlled by bits in DACRn.
31
Field BA
Reset Uninitialized
R/W
Address
Figure 15-3. DRAM Address and Control Register (DACRn)
Table 15-5 describes DACRn fields.
Bit Name
31–18 BA Base address register. With DCMR[BAM], determines the address range in which the associated DRAM block is
located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits
match, the address hits in the associated DRAM block. BA functions the same as in asynchronous operation.
17–16 — Reserved, should be cleared.
15 RE Refresh enable. Determines when the DRAM controller generates a refresh cycle to the DRAM block.
0 Do not refresh associated DRAM block
1 Refresh associated DRAM block
14 — Reserved, should be cleared.
13–12 CASL CAS latency. Affects the following SDRAM timing specifications. Timing nomenclature varies with
manufacturers. Refer to the SDRAM specification for the appropriate timing nomenclature:
t —SRAS assertion to SCAS assertion
RCD
t —SCAS assertion to data out
CASL
t —
ACTV
RAS
t —Precharge command to
RP
t t
,
RWL RDL
t —Last data out to precharge command
EP
11 — Reserved, should be cleared.
15-6
18 17 16
—
IPSBAR+0x048 (DACR0); 0x050 (DACR1)
Table 15-5. DACRn Field Descriptions
Parameter
command to precharge command
command
ACTV
—Last data input to precharge command
MCF5282 User's Manual
15 14 13 12 11 10
RE — CASL — CBM
0 Uninitialized
R/W
Description
Number of Bus Clocks
CASL= 00 CASL = 01
1
1
2
1
1
1
9 8 7 6 5 4 3
— IMRS PS IP
0 Uninitialized
CASL= 10 CASL= 11
2 3
2 3
4 6
2 3
1 1
1 1
MOTOROLA
2 0
—
3
3
6
3
1
1