Mitsubishi Electric AJ71C24-S6 User Manual page 286

APPENDICES
MELSEC-A
1.3
Function Comparison
\
Module
Function
-
See
Section
Xn7 of the 1 1 0 signals for the PC
CPU is used as the READY signal.
Module READY signal
4lways checked.
Set whether or not the AJ71 C24-S6
checks the CD signal.
RS-232C CD terminal check
I
Since the ONIOFF status of the
error LED is stored in buffer
memory, communications errors
can be checked with the PC CPU
by reading the buffer memory with
a sequence program.
The request signai to turn the error
display OFF can be output with
a
sequence program.
Error occurrence is
:onfirmed by the
.ED on the front
>anel of the module.
Display area
rransmission error
nformation
the error
display
The PC CPU must
, e reset.
-
Com-
mand
Batch read
Y
Extension file registers (R)
are
read in units of each register.
Data is written to extension file
registers (R) in units of each
register.
To write data, block numbers and
device numbers
are
designated for
the extension file registers (R) at
random in units of each register.
The extension file registers (R) t o
be monitored are set in units of
each moister.
Batch write
I
EW
Exten-
sion file
registers
Micro-
computer
program
Com-
ment
rest
(random write)
Monitor data EM
registration
Monitor
IIE
-
The extension file registers
(R),
set
for monitoring, are monitored.
Main microcomputer program is
read.
Sub microcomputer program is
read.
Main microcomputer program is
written.
Sub microcomputer program is
written.
Comments are read from memory.
Comments are written t o memory.
The send request can be output
from the PC CPU for data
transmission with dedicated
protocols 1 to 4.
Batch
read
edi-
ated
rotoco
to 4
-
Batch
write
Batch read
Batch write
)ata transmission
itart is controlled by
he computer.
:ommunications is
)ossibie only with
he PC CPU which
s loaded with the
\J71 C24.
Communications is possible with a
PC CPU which is not loaded with
the AJ71C24 in MELSECNET.
Communications with the PC CPU
in MELSECNET
Using AnACPU dedicated
commands, data communications
is possible with all device
memories, extension file registers,
and extension comments of an
A2AIA3ACPU.
Data communications using
AnACPU dedicated commands
with an A2ACPU(-S1) and A3ACPU.
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APP
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