Qsfp28 Module Connectors; I2C Bus - Xilinx Alveo U200 User Manual

QSFP28 Module Connectors

The Alveo accelerator cards host two 4-lane small form-factor pluggable (QSFP) connectors that
accept an array of optical modules. Each connector is housed within a single QSFP cage
assembly.
The QSFP+ connectors are accessible via the I2C interface on the Alveo U200/U250 accelerator
cards. The QSFP connector's sideband signals are accessible directly from the FPGA. The
MODSELL, RESETL, MODPRSL, INTL, and LPMODE sideband signals are defined in the small
form factor (SFF) specifications listed below. The components visible through the card PCIe
panel/bracket top to bottom are:
• Triple status LEDs
• QSFP0
• QSFP1
• USB
For additional information about the quad SFF pluggable (28 Gb/s QSFP+) module, see the
SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ at the SNIA Technology Affiliates
website: https:/ /www.snia.org/sff/specifications2.
Each QSFP connector has its own clock generator.
• QSFP0 clock
Clock generator: Silicon Labs SI5335A-B06201-GM
○
Output CLK1A/1B: the QSFP0_CLOCK_P/N clock is an AC-coupled LVDS 156.25 MHz
○
clock wired to the QSFP0 GTY interface
• QSFP1 clock
Clock generator: Silicon Labs SI5335A-B06201-GM
○
Output CLK1A/1B: the QSFP1_CLOCK_P/N clock is an AC-coupled LVDS 156.25 MHz
○
clock wired to the QSFP1 GTY interface
The detailed FPGA and QSFP pin connections for the feature described in this section are
documented in the

I2C Bus

The Alveo U200/U250 accelerator cards implement an I2C bus network (the device tree details
are available in the board support package).
UG1289 (v1.1.1) November 20, 2019
Alveo U200 and U250 Accelerator Cards
Appendix A: Xilinx Design Constraints (XDC)
Chapter 3: Card Component Description
File.
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