Usb Jtag Interface; Ft4232Hq Usb-Uart Interface; Pci Express Endpoint - Xilinx Alveo U200 User Manual

• Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: variable
For more flash memory details, see the Micron MT25QU01GBBB8E12-0SIT data sheet at the
Micron website.
For configuration details, see the UltraScale Architecture Configuration User Guide (UG570). The
detailed FPGA and Flash pin connections for the feature described in this section are
documented in the Alveo U200/U250 accelerator card XDC file, referenced in
Design Constraints (XDC)

USB JTAG Interface

The Alveo accelerator card provides access to the FPGA device via the JTAG interface.
FPGA configuration is available through the Vivado
board USB-to-JTAG FT4232HQ bridge device. The micro-AB USB connector on the Alveo U200/
U250 accelerator card PCIe
Note: JTAG configuration is allowed at any time regardless of the FPGA mode pin settings consistent with
the UltraScale Architecture Configuration User Guide (UG570).
For more details about the FT4232HQ device, see the FTDI website:

FT4232HQ USB-UART Interface

The FT4232HQ Quad USB-UART provides a UART connection through the micro-AB USB
connector. The FPGA UART TX/RX (two-wire) connection is made through the FT4232HQ BD
port. Channel BD implements a 2-wire level-shifted TX/RX UART connection to the FPGA. The
FTDI FT4232HQ data sheet is available on the FTDI website:

PCI Express Endpoint

The Alveo U200/U250 accelerator card implements a 16-lane PCI Express
performs data transfers at the rate of 2.5 giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for
Gen2, and 8.0 GT/s for Gen3 applications. The -2 speed grade FPGA included with the cards
supports up to Gen3 x16.
UG1289 (v1.1.1) November 20, 2019
Alveo U200 and U250 Accelerator Cards
File.
®
panel/bracket provides external device programming access.
Chapter 3: Card Component Description
® hardware manager, which accesses the on-
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Appendix A: Xilinx
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edge connector that
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