Fpga Configuration - Xilinx Alveo U200 User Manual

FPGA Configuration

The Alveo U200/U250 accelerator card supports two UltraScale+™ FPGA configuration modes:
• Quad SPI flash memory
• JTAG using USB JTAG configuration port (USB J13/FT4232H U27)
The FPGA bank 0 mode pins are hardwired to M[2:0] = 001 master SPI mode with pull-up/down
resistors.
At power up, the FPGA is configured by the Quad SPI NOR flash device (Micron
MT25QU01GBBA8E12-0SIT) with the FPGA_CCLK operating at clock rate of 105 MHz
(EMCCLK) using the master serial configuration mode. The Quad SPI flash memory NOR device
has a capacity of 1 Gb.
If the JTAG cable is plugged in, QSPI configuration might not occur. JTAG mode is always
available independent of the mode pin settings.
For complete details on configuring the FPGA, see the UltraScale Architecture Configuration User
Guide (UG570).
Table 2: Configuration Modes
Configuration Mode
Master SPI
JTAG
UG1289 (v1.1.1) November 20, 2019
Alveo U200 and U250 Accelerator Cards
M[2:0]
001
Not applicable – JTAG overrides
Chapter 2: Card Installation and Configuration
Bus Width
x1, x2, x4
x1
Send Feedback
CCLK Direction
FPGA output
Not applicable
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