Input Signal Control Pins - Huawei MU739 Hardware Manual

HUAWEI MU739 HSPA+ LGA Module
Hardware Guide

3.4.2 Input Signal Control Pins

The MU739 module implements power-on and resets the hardware through the input
signal control pins. The power-on and reset control parts of the interface of the MU739
module include ON1, ON2_N interfaces signal and the baseband reset interface
signal RESIN_N and the system reset signal PWRDWN_N.
The ON1 and ON2_N pins are used to implement turning on the module. The ON1 is
high active and the ON2_N is low active.
ON1 can also be controlled by a host processor GPIO (with internal pull-down under
reset).ON2_N can also be controlled by a host processor GPIO (with internal pull-up
under reset), when tied to GND this input can be used to force an automatic boot up
when power is applied or after a hard reset is performed.
Figure 3-3 Connections of ON1 and ON2_N pins
The PWRDWN_N pin is used to power down the module. When the software stops
responding, the PWRDWN_N pin can be pulled down for at least 20 ms to reset the
complete system (baseband, PMU and RF) into initial state.
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The RESIN_ N pin is used to reset the baseband with some delay. It delays the turn
down to put critical blocks like EBU into a safe state before performing the reset.
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Issue 01 (2011-08-24)
Active low with internal pull-up (200 KΩ)
Initiate power down of the modem system (baseband, PMU, RF & clocks)
All PMU LDOs are turned off except RTC LDO and PMU LDO. The PMU remains
ready to handle an ON-event.
Active low without Pull-up or pull-down
Resets baseband sub-system.
Existing LDOs which are enabled remain enabled, disabled LDOs will power up.
The 26 MHz clock from SMARTi-UE2 continues to be distributed according to the
corresponding enable control signals.
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Description of the Application Interfaces
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