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PQA4
PQA0
10-bit A/D Converter
PQB3
PQB0
V
RH
V
RL
V
DDA
Analog
V
Power
SSA
Figure 27-19. QADC Analog Subsystem Block Diagram
27.7.3.2 Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution
time. Initial sample time refers to the time during which the selected input channel is
coupled through the sample buffer amplifier to the sample capacitor. The sample buffer is
used to quickly reproduce its input signal on the sample capacitor and minimize charge
sharing errors. During the final sampling period the amplifier is bypassed, and the
multiplexer input charges the sample capacitor array directly for improved accuracy.
During the resolution period, the voltage in the sample capacitor is converted to a digital
value and stored in the SAR as shown in Figure 27-20.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16
QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is 10
QCLK cycles.
A conversion requires a minimum of 14 QCLK cycles (7 µs with a 2.0-MHz QCLK). If the
maximum final sample time period of 16 QCLKs is selected, the total conversion time is
28 QCLKs or 14 µs (with a 2.0-MHz QCLK).
MOTOROLA
16
Chan. Decode & MUX
16:1
Input
Sample
Buffer
CSAMP
10
Compar-
ator
Chapter 27. Queued Analog-to-Digital Converter (QADC)
4
6
Bias Circuit
Power-
Internal
Channel
Down
Decode
State Machine & Logic
SAR Timing
10
10
Successive
Approximation
Register
Functional Description
CHAN[5:0]
STOP
RST
QCLK
2
IST
Start Conv
End OF Conv
SAR[9:0]
27-35
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