Table of Contents
Advertisement
The feedback clock comes from one of the following:
• CLKOUT in 1:1 PLL mode
• VCO output divided by two if CLKOUT is disabled in 1:1 PLL mode
• VCO output divided by the MFD in normal PLL mode
When the frequency of the feedback clock equals the frequency of the reference clock, the
PLL is frequency-locked. If the falling edge of the feedback clock lags the falling edge of
the reference clock, the PFD pulses the UP signal. If the falling edge of the feedback clock
leads the falling edge of the reference clock, the PFD pulses the DOWN signal. The width
of these pulses relative to the reference clock depends on how much the two clocks lead or
lag each other. Once phase lock is achieved, the PFD continues to pulse the UP and DOWN
signals for very short durations during each reference clock cycle. These short pulses
continually update the PLL and prevent the frequency drift phenomenon known as
dead-banding.
9.7.4.2
Charge Pump/Loop Filter
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current
magnitude of the charge pump varies with the MFD as shown in Table 9-8.
Table 9-8. Charge Pump Current and MFD in Normal Mode Operation
The UP and DOWN signals from the PFD control whether the charge pump applies or
removes charge, respectively, from the loop filter. The filter is integrated on the chip.
9.7.4.3
Voltage Control Output (VCO)
The voltage across the loop filter controls the frequency of the VCO output. The
frequency-to-voltage relationship (VCO gain) is positive, and the output frequency is four
times the target system frequency.
9.7.4.4
Multiplication Factor Divider (MFD)
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the VCO and feeds
it back to the PFD. The PFD controls the VCO frequency via the charge pump and loop
filter such that the reference and feedback clocks have the same frequency and phase. Thus,
the frequency of the input to the MFD, which is also the output of the VCO, is the reference
frequency multiplied by the same amount that the MFD divides by. For example, if the
MFD divides the VCO frequency by six, the PLL is frequency locked when the VCO
MOTOROLA
Charge Pump Current
1X
2X
4X
Chapter 9. Clock Module
Functional Description
MFD
0 ≤ MFD < 2
2 ≤ MFD < 6
6 ≤ MFD
9-13
Advertisement
Table of Contents
