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DMA Timer Programming Model
Table 21-3 describes the DTXMRn fields.
Bits
Name
7
DMAEN
DMA request. Enables DMA request output on counter reference match or capture edge event.
0 DMA request disabled
1 DMA request enabled
6–1
—
Reserved, should be cleared.
0
MODE16 Selects the increment mode for the timer. MODE16 = 1 is intended to exercise the upper bits of the 32-bit timer
in diagnostic software without requiring the timer to count through its entire dynamic range. This bit puts
the timer in a 16-bit mode in which only the upper 16 bits of the DTCN, DTRR, and DTCR are applicable
to the timer function.
0 Increment timer by 1
1 Increment timer by 65,537
21.2.8 DMA Timer Event Registers (DTERn)
DTERs, shown in Figure 21-4, reports capture or reference events by setting DTERn[CAP]
or DTERn[REF]. This reporting is done regardless of the corresponding DMA request or
interrupt enable values, DTXMRn[DMAEN] and DTMRn[ORRI,CE].
Writing a 1 to either DTERn[REF] or DTERn[CAP] clears it (writing a 0 does not affect
bit value); both bits can be cleared at the same time. If configured to generate an interrupt
request, the REF and CAP bits must be cleared early in the interrupt service routine so the
timer module can negate the IRQn request signal to the interrupt controller. If configured
to generate a DMA request, the processing of the DMA data transfer automatically clears
both the REF and CAP flags via the internal DMA ACK signal.
Field
Reset
R/W
Address IPSBAR + 0x403 (DTER0); + 0x443 (DTER1); 0x483 (DTER2); + 0x4C3 (DTER3)
21-6
DTXMR
Table 21-3.
7
—
R/W (ones clear/zeros have no effect)
Figure 21-4. DTERn Bit Definitions
MCF5282 User's Manual
n Field Descriptions
Description
2
0000_0000
1
0
REF
CAP
MOTOROLA
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