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System Access Control Unit (SACU)
Table 8-12. Peripheral Access Control Registers (PACRs) (continued)
IPSBAR Offset
0x027
0x028
0x029
0x02a
0x02b
0x02c
0x02d
0x02e
At reset, these on-chip modules are configured to have only supervisor read/write access
capabilities. If an instruction fetch access to any of these peripheral modules is attempted,
the IPS bus cycle is immediately terminated with an error.
8.6.3.3
Grouped Peripheral Access Control Registers
(GPACR0 and GPACR1)
The on-chip peripheral space starting at IPSBAR is subdivided into sixteen 64-Mbyte
regions. Each of the first two regions has a unique access control register associated with
it. The other fourteen regions are in reserved space; the access control registers for these
regions are not implemented. Bits [29:26] of the address select the specific GPACRn to be
used for a given reference within the IPS address space. These access control registers are
8 bits in width so that read, write, and execute attributes may be assigned to the given IPS
region.
The access control for modules with memory space protected
by PACR0–PACR8 are determined by the PACR0–PACR8
settings. The access control is not affected by GPACR0, even
though the modules are mapped in its 64-Mbyte address space.
Field
Reset
Read/Write
Address
8-18
Name
PACR3
PACR4
—
PACR5
PACR6
PACR7
—
PACR8
NOTE
7
6–4
LOCK
—
R/W
R
IPSBAR + 0x030, IPSBAR + 0x31
Figure 8-10. GPACR Register
MCF5282 User's Manual
Modules Controlled
ACCESS_CTRL1
UART2
2
I
C
—
DTIM0
DTIM2
INTC0
—
FEC0
3
ACCESS_CTRL
0000_0000
R/W
ACCESS_CTRL0
—
QSPI
—
DTIM1
DTIM3
INTC1
—
—
0
MOTOROLA
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